1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  6. entity round_constant is
  7. port
  8. (
  9. CLK : in std_logic;
  10. key_load: in std_logic;
  11. rcon: out std_logic_vector(31 downto 0)
  12. );
  14. attribute SIGIS : string;
  15. attribute SIGIS of CLK : signal is "Clk";
  17. end round_constant;
  19. architecture EXAMPLE of key_expansion is
  21. signal rcnt_next, rcnt: integer := 0;
  22. signal rcon : std_logic_vector(31 downto 0) := (OTHERS => '0');
  24. begin
  27. process(clk)
  28. begin
  30. if rising_edge(clk) then
  31. if(key_load = '1') then
  32. rcon <= x"01000000";
  33. rcnt <= 0;
  34. else
  35. rcnt <= rcnt_next;
  36. end if;
  37. end if;
  38. end process;
  40. rcnt_next <= rcnt + 1;
  43. process(rcnt_next)
  44. begin
  46. case(rcnt_next) is
  47. when 0 => rcon <= x"01_00_00_00";
  48. when 1 => rcon <= x"02_00_00_00";
  49. when 2 => rcon <= x"04_00_00_00";
  50. when 3 => rcon <= x"08_00_00_00";
  51. when 4 => rcon <= x"10_00_00_00";
  52. when 5 => rcon <= x"20_00_00_00";
  53. when 6 => rcon <= x"40_00_00_00";
  54. when 7 => rcon <= x"80_00_00_00";
  55. when 8 => rcon <= x"1b_00_00_00";
  56. when 9 => rcon <= x"36_00_00_00";
  57. when OTHERS => rcon <= x"00_00_00_00";
  58. end case;
  60. end process;
  62. end architecture EXAMPLE;

round_constant.vhd