1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  5. entity key_expansion_tb is
  6. end key_expansion_tb;
  8. architecture tb of key_expansion_tb is
  10. component key_expansion
  11. port (CLK : in std_logic;
  12. key_load : in std_logic;
  13. key : in std_logic_vector (127 downto 0);
  14. xkey0 : out std_logic_vector (31 downto 0);
  15. xkey1 : out std_logic_vector (31 downto 0);
  16. xkey2 : out std_logic_vector (31 downto 0);
  17. xkey3 : out std_logic_vector (31 downto 0));
  18. end component;
  20. -- Input
  21. signal CLK : std_logic;
  22. signal key_load : std_logic;
  23. signal key : std_logic_vector (127 downto 0) := x"10_11_12_13_14_15_16_17_18_19_1a_1b_1c_1d_1e_1f";
  25. -- Output
  26. signal xkey0 : std_logic_vector (31 downto 0);
  27. signal xkey1 : std_logic_vector (31 downto 0);
  28. signal xkey2 : std_logic_vector (31 downto 0);
  29. signal xkey3 : std_logic_vector (31 downto 0);
  31. constant TbPeriod : time := 10 ns; -- EDIT put right period here
  32. signal TbClock : std_logic := '0';
  34. begin
  36. dut : key_expansion
  37. port map (CLK => CLK,
  38. key_load => key_load,
  39. key => key,
  40. xkey0 => xkey0,
  41. xkey1 => xkey1,
  42. xkey2 => xkey2,
  43. xkey3 => xkey3);
  45. TbClock <= not TbClock after TbPeriod/2;
  47. -- EDIT: Check that CLK is really your main clock signal
  48. CLK <= TbClock;
  50. stimuli : process
  51. begin
  52. key_load <= '0';
  53. wait for 20 ns;
  54. key_load <= '1';
  55. wait for 10 ns;
  56. key_load <= '0';
  57. wait for 500 ns;
  59. --wait;
  60. report "End of Simulation" severity failure;
  61. --finish(2);
  62. end process;
  64. end tb;

key_expansion_tb.vhd