[dell@localhost verilog]$ yosys -p *.v

/----------------------------------------------------------------------------\

| |

| yosys -- Yosys Open SYnthesis Suite |

| |

| Copyright (C) 2012 - 2015 Clifford Wolf <[email protected]> |

| |

| Permission to use, copy, modify, and/or distribute this software for any |

| purpose with or without fee is hereby granted, provided that the above |

| copyright notice and this permission notice appear in all copies. |

| |

| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |

| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |

| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |

| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |

| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |

| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |

| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |

| |

\----------------------------------------------------------------------------/

Yosys 0.5 (git sha1 UNKNOWN, clang 3.8.1 -fPIC -Os)

-- Parsing `mor1kx_branch_predictor_gshare.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_branch_predictor_gshare.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_branch_predictor_gshare'.

Warning: Replacing memory \state with list of registers. See mor1kx_branch_predictor_gshare.v:86, mor1kx_branch_predictor_gshare.v:70

Successfully finished Verilog frontend.

-- Parsing `mor1kx_branch_predictor_saturation_counter.v' using frontend `verilog' --

2. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_branch_predictor_saturation_counter.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_branch_predictor_saturation_counter'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_branch_predictor_simple.v' using frontend `verilog' --

3. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_branch_predictor_simple.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_branch_predictor_simple'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_bus_if_wb32.v' using frontend `verilog' --

4. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_bus_if_wb32.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_bus_if_wb32'.

Warning: Ignoring call to system task $display at mor1kx_bus_if_wb32.v:57.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cache_lru.v' using frontend `verilog' --

5. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cache_lru.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_cache_lru'.

Warning: Replacing memory \expand with list of registers. See mor1kx_cache_lru.v:177, mor1kx_cache_lru.v:171

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cfgrs.v' using frontend `verilog' --

6. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cfgrs.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_cfgrs'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cpu_cappuccino.v' using frontend `verilog' --

7. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cpu_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_cpu_cappuccino'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cpu_espresso.v' using frontend `verilog' --

8. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cpu_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_cpu_espresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cpu_prontoespresso.v' using frontend `verilog' --

9. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cpu_prontoespresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_cpu_prontoespresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_cpu.v' using frontend `verilog' --

10. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_cpu.v' to AST representation.

Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.

Yosys does support them but it is recommended to use `ifdef constructs instead!

Generating RTLIL representation for module `\mor1kx_cpu'.

-- Parsing `mor1kx_ctrl_cappuccino.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_ctrl_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_ctrl_cappuccino'.

-- Parsing `mor1kx_ctrl_espresso.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_ctrl_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_ctrl_espresso'.

-- Parsing `mor1kx_ctrl_prontoespresso.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_ctrl_prontoespresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_ctrl_prontoespresso'.

-- Parsing `mor1kx_dcache.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_dcache.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_dcache'.

-- Parsing `mor1kx_decode_execute_cappuccino.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_decode_execute_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_decode_execute_cappuccino'.

-- Parsing `mor1kx_decode.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_decode.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_decode'.

-- Parsing `mor1kx-defines.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx-defines.v' to AST representation.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_dmmu.v' using frontend `verilog' --

18. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_dmmu.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_dmmu'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_execute_alu.v' using frontend `verilog' --

19. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_execute_alu.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_execute_alu'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_execute_ctrl_cappuccino.v' using frontend `verilog' --

20. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_execute_ctrl_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_execute_ctrl_cappuccino'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_fetch_cappuccino.v' using frontend `verilog' --

21. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_fetch_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_fetch_cappuccino'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_fetch_espresso.v' using frontend `verilog' --

22. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_fetch_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_fetch_espresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_fetch_prontoespresso.v' using frontend `verilog' --

23. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_fetch_prontoespresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_fetch_prontoespresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_fetch_tcm_prontoespresso.v' using frontend `verilog' --

24. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_fetch_tcm_prontoespresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_fetch_tcm_prontoespresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_icache.v' using frontend `verilog' --

25. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_icache.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_icache'.

Warning: Replacing memory \tag_way_in with list of registers. See mor1kx_icache.v:327

Successfully finished Verilog frontend.

-- Parsing `mor1kx_immu.v' using frontend `verilog' --

26. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_immu.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_immu'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_lsu_cappuccino.v' using frontend `verilog' --

27. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_lsu_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_lsu_cappuccino'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_lsu_espresso.v' using frontend `verilog' --

28. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_lsu_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_lsu_espresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_pic.v' using frontend `verilog' --

29. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_pic.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_pic'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_rf_cappuccino.v' using frontend `verilog' --

30. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_rf_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_rf_cappuccino'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_rf_espresso.v' using frontend `verilog' --

31. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_rf_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_rf_espresso'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx_simple_dpram_sclk.v' using frontend `verilog' --

32. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx_simple_dpram_sclk.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_simple_dpram_sclk'.

Successfully finished Verilog frontend.

-- Parsing `mor1kx-sprs.v' using frontend `verilog' --

33. Executing Verilog-2005 frontend.

Parsing Verilog input from `mor1kx-sprs.v' to AST representation.

-- Parsing `mor1kx_store_buffer.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_store_buffer.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_store_buffer'.

-- Parsing `mor1kx_ticktimer.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_ticktimer.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_ticktimer'.

-- Parsing `mor1kx_true_dpram_sclk.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_true_dpram_sclk.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_true_dpram_sclk'.

-- Parsing `mor1kx.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx.v' to AST representation.

Generating RTLIL representation for module `\mor1kx'.

-- Parsing `mor1kx_wb_mux_cappuccino.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_wb_mux_cappuccino.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_wb_mux_cappuccino'.

-- Parsing `mor1kx_wb_mux_espresso.v' using frontend `verilog' --

Parsing Verilog input from `mor1kx_wb_mux_espresso.v' to AST representation.

Generating RTLIL representation for module `\mor1kx_wb_mux_espresso'.

-- Running command `mor1kx_branch_prediction.v' --

ERROR: No such command: mor1kx_branch_prediction.v (type 'help' for a command overview)

[dell@localhost verilog]$ ls

mor1kx_branch_prediction.v mor1kx_cpu_cappuccino.v mor1kx_dcache.v mor1kx_fetch_cappuccino.v mor1kx_lsu_espresso.v mor1kx_ticktimer.v

mor1kx_branch_predictor_gshare.v mor1kx_cpu_espresso.v mor1kx_decode_execute_cappuccino.v mor1kx_fetch_espresso.v mor1kx_pic.v mor1kx_true_dpram_sclk.v

mor1kx_branch_predictor_saturation_counter.v mor1kx_cpu_prontoespresso.v mor1kx_decode.v mor1kx_fetch_prontoespresso.v mor1kx_rf_cappuccino.v mor1kx_utils.vh

mor1kx_branch_predictor_simple.v mor1kx_cpu.v mor1kx-defines.v mor1kx_fetch_tcm_prontoespresso.v mor1kx_rf_espresso.v mor1kx.v

mor1kx_bus_if_wb32.v mor1kx_ctrl_cappuccino.v mor1kx_dmmu.v mor1kx_icache.v mor1kx_simple_dpram_sclk.v mor1kx_wb_mux_cappuccino.v

mor1kx_cache_lru.v mor1kx_ctrl_espresso.v mor1kx_execute_alu.v mor1kx_immu.v mor1kx-sprs.v mor1kx_wb_mux_espresso.v

mor1kx_cfgrs.v mor1kx_ctrl_prontoespresso.v mor1kx_execute_ctrl_cappuccino.v mor1kx_lsu_cappuccino.v mor1kx_store_buffer.v pfpu32

[dell@localhost verilog]$