1. /************************************************
  2. The Verilog HDL code example is from the book
  3. Computer Principles and Design in Verilog HDL
  4. by Yamin Li, published by A JOHN WILEY & SONS
  5. ************************************************/
  6. module goldschmidt (a,b,start,clk,clrn,q,busy,ready,count,yn);
  7. input [31:0] a; // dividend: .1xxx...x
  8. input [31:0] b; // divisor: .1xxx...x
  9. input start; // start
  10. input clk, clrn; // clock and reset
  11. output [31:0] q; // quotient: x.xxx...x
  12. output reg busy; // busy
  13. output reg ready; // ready
  14. output [2:0] count; // counter
  15. output [31:0] yn; // .11111...1
  16. reg [63:0] reg_a; // x.xxxx...x
  17. reg [63:0] reg_b; // 0.xxxx...x
  18. reg [2:0] count;
  19. wire [63:0] two_minus_yi = ~reg_b + 1'b1; // 1.xxxx...x (2 - yi)
  20. wire [127:0] xi = reg_a * two_minus_yi; // 0x.xxx...x
  21. wire [127:0] yi = reg_b * two_minus_yi; // 0x.xxx...x
  22. assign q = reg_a[63:32] + |reg_a[31:29]; // rounding up
  23. assign yn = reg_b[62:31];
  24. always @ (posedge clk or negedge clrn) begin
  25. if (!clrn) begin
  26. busy <= 0;
  27. ready <= 0;
  28. end else begin
  29. if (start) begin
  30. reg_a <= {1'b0,a,31'b0}; // 0.1x...x0...0
  31. reg_b <= {1'b0,b,31'b0}; // 0.1x...x0...0
  32. busy <= 1;
  33. ready <= 0;
  34. count <= 0;
  35. end else begin
  36. reg_a <= xi[126:63]; // x.xxx...x
  37. reg_b <= yi[126:63]; // 0.xxx...x
  38. count <= count + 3'b1; // count++
  39. if (count == 3'h4) begin // finish
  40. busy <= 0;
  41. ready <= 1; // q is ready
  42. end
  43. end
  44. end
  45. end
  46. endmodule

goldschmidt.v