- [phung@localhost OpenRISC]$ fusesoc sim mor1kx-generic --elf-load hello.elf
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::wb_intercon:1.0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::wb_intercon:0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::fifo:1.0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::ram_wb:0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::vlog_tb_utils:0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::wb_sdram_ctrl:0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::wb_altera_ddr_wrapper:0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::stream_utils:1.0
- WARN: plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ::elf-loader:0
- WARN: Unknown section 'dpi' in '/home/phung/Documents/Grive/Personal/Digital/OpenRISC/OpTiMSoC/2016.1/external/extra_cores/cores/uartdpi/uartdpi.core'
- WARN: Failed to parse /home/phung/Documents/Grive/Personal/Digital/OpenRISC/OpTiMSoC/2016.1/external/extra_cores/boards/arty/arty-ddr.core: Unknown file type 'data'. Allowed file types are QIP, SDC, tclSource, user, verilogSource, verilogSource-95, verilogSource-2001, verilogSource-2005, systemVerilogSource, systemVerilogSource-3.0, systemVerilogSource-3.1, systemVerilogSource-3.1a, vhdlSource, vhdlSource-87, vhdlSource-93, vhdlSource-2008, xci, xdc
- WARN: Failed to parse /home/phung/Documents/Grive/Personal/Digital/OpenRISC/OpTiMSoC/2016.1/external/extra_cores/boards/nexys4ddr/nexys4ddr-ddr.core: Unknown file type 'data'. Allowed file types are QIP, SDC, tclSource, user, verilogSource, verilogSource-95, verilogSource-2001, verilogSource-2005, systemVerilogSource, systemVerilogSource-3.0, systemVerilogSource-3.1, systemVerilogSource-3.1a, vhdlSource, vhdlSource-87, vhdlSource-93, vhdlSource-2008, xci, xdc
- INFO: Preparing ::adv_debug_sys:0
- INFO: Downloading olofk/adv_debug_sys from github
- INFO: Preparing ::elf-loader:0
- INFO: Preparing ::jtag_tap:1.13
- INFO: Downloading olofk/jtag from github
- INFO: Preparing ::jtag_vpi:0-r2
- INFO: Downloading fjullien/jtag_vpi from github
- INFO: Preparing ::mor1kx:4.1
- INFO: Downloading openrisc/mor1kx from github
- INFO: Preparing ::uart16550:1.5.4
- INFO: Downloading olofk/uart16550 from github
- INFO: Preparing ::verilog-arbiter:0-r1
- INFO: Downloading bmartini/verilog-arbiter from github
- INFO: Preparing ::verilog_utils:0
- INFO: Preparing ::vlog_tb_utils:1.0
- INFO: Preparing ::wb_common:0
- INFO: Preparing ::wb_bfm:1.0
- INFO: Downloading olofk/wb_bfm from github
- INFO: Preparing ::wb_intercon:1.0
- INFO: Downloading olofk/wb_intercon from github
- INFO: Preparing ::wb_ram:1.0
- INFO: Preparing ::mor1kx-generic:0
- INFO: Running /home/phung/.local/share/orpsoc-cores/cores/elf-loader/check_libelf.sh
- Compiling ../src/elf-loader_0/elf-loader.c...
- Compiling ../src/elf-loader_0/vpi_wrapper.c...
- Making elf-loader_0.vpi from elf-loader.o vpi_wrapper.o...
- Compiling ../src/jtag_vpi_0-r2/jtag_vpi.c...
- Making jtag_vpi_0-r2.vpi from jtag_vpi.o...
- orpsoc_tb.dut.mor1kx0.bus_gen.ibus_bridge: Wishbone bus IF is B3_REGISTERED_FEEDBACK
- orpsoc_tb.dut.mor1kx0.bus_gen.dbus_bridge: Wishbone bus IF is B3_REGISTERED_FEEDBACK
- Program header 0: addr 0x00000000, size 0x00007504
- Program header 1: addr 0x00009504, size 0x00000894
- elf-loader: /home/phung/Documents/Grive/Personal/Digital/OpenRISC/hello.elf was loaded
- Loading 10086 words
- 0 : Illegal Wishbone B3 cycle type (xxx)
- Hello world, from an OpenRISC system!