1. [promach@localhost parallella-fpga]$ make
  2. make -C AdiHDLLib/ lib
  3. make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
  4. make -C library/ all
  5. make[2]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
  6. make -C axi_clkgen
  7. make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
  8. rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
  9. vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
  10. make[3]: *** [Makefile:44: axi_clkgen.xpr] Error 1
  11. make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
  12. make[2]: [Makefile:96: lib] Error 2 (ignored)
  13. make -C axi_hdmi_tx
  14. make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
  15. rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
  16. vivado -mode batch -source axi_hdmi_tx_ip.tcl >> axi_hdmi_tx_ip.log 2>&1
  17. make[3]: *** [Makefile:56: axi_hdmi_tx.xpr] Error 1
  18. make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
  19. make[2]: [Makefile:97: lib] Error 2 (ignored)
  20. make -C axi_spdif_tx
  21. make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
  22. rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
  23. vivado -mode batch -source axi_spdif_tx_ip.tcl >> axi_spdif_tx_ip.log 2>&1
  24. make[3]: *** [Makefile:46: axi_spdif_tx.xpr] Error 1
  25. make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
  26. make[2]: [Makefile:98: lib] Error 2 (ignored)
  27. make[2]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
  28. make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
  29. make -C oh/src/parallella/fpga/parallella_base all
  30. make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
  31. vivado -mode batch -source run.tcl
  33. ****** Vivado v2016.2 (64-bit)
  34. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  35. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  36. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  38. source run.tcl
  39. # source ./system_params.tcl
  40. ## set design parallella_base
  41. ## set projdir ./
  42. ## set root "../../.."
  43. ## set partname "xc7z020clg400-1"
  44. ## set hdl_files [list \
  45. ## $root/parallella/hdl \
  46. ## $root/common/hdl/ \
  47. ## $root/emesh/hdl \
  48. ## $root/emmu/hdl \
  49. ## $root/axi/hdl \
  50. ## $root/emailbox/hdl \
  51. ## $root/edma/hdl \
  52. ## $root/elink/hdl \
  53. ## ]
  54. ## set ip_files [list \
  55. ## $root/xilibs/ip/fifo_async_104x32.xci \
  56. ## ]
  57. ## set constraints_files []
  58. # source ../../../common/fpga/create_ip.tcl
  59. ## create_project -force $design $projdir -part $partname
  60. ## set_property target_language Verilog [current_project]
  61. ## set_property source_mgmt_mode None [current_project]
  62. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  63. ## create_fileset -srcset sources_1
  64. ## }
  65. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  66. ## set_property top $design [get_filesets sources_1]
  67. ## if {[string equal [get_filesets -quiet constraints_1] ""]} {
  68. ## create_fileset -constrset constraints_1
  69. ## }
  70. ## if {[llength $constraints_files] != 0} {
  71. ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
  72. ## }
  73. ## if {[llength $ip_files] != 0} {
  74. ##
  75. ## #Add to fileset
  76. ## add_files -norecurse -fileset [get_filesets sources_1] $ip_files
  77. ##
  78. ## #Set mode for IP
  79. ## foreach file $ip_files {
  80. ## #TODO: is this needed?
  81. ## set file_obj [get_files -of_objects [get_filesets sources_1] $file]
  82. ## set_property "synth_checkpoint_mode" "Singular" $file_obj
  83. ## }
  84. ## #RERUN/UPGRADE IP
  85. ## upgrade_ip [get_ips]
  86. ## }
  87. INFO: [IP_Flow 19-234] Refreshing IP repositories
  88. INFO: [IP_Flow 19-1704] No user IP repositories specified
  89. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
  90. WARNING: [IP_Flow 19-2162] IP 'fifo_async_104x32' is locked:
  91. * IP definition 'FIFO Generator (12.0)' for IP 'fifo_async_104x32' has a newer major version in the IP Catalog.
  92. * IP definition 'FIFO Generator (12.0)' for IP 'fifo_async_104x32' has a different revision in the IP Catalog.
  93. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
  94. ERROR: [Common 17-107] Cannot change read-only property 'synth_checkpoint_mode'.
  95. Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.
  97. while executing
  98. "source ../../../common/fpga/create_ip.tcl"
  99. (file "run.tcl" line 4)
  100. INFO: [Common 17-206] Exiting Vivado at Tue Dec 13 08:53:26 2016...
  101. make[1]: *** [Makefile:18: all] Error 1
  102. make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
  103. make: *** [Makefile:8: all] Error 2