1. [promach@localhost oh]$ cd src/accelerator/fpga/
  2. [promach@localhost fpga]$ ./build.sh
  3. rm: cannot remove 'system_wrapper.bit.bin': No such file or directory
  4. rm: cannot remove 'bit2bin.bin': No such file or directory
  6. ****** Vivado v2016.2 (64-bit)
  7. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  8. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  9. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  11. source package.tcl
  12. # source ./ip_params.tcl
  13. ## set design axi_accelerator
  14. ## set projdir ./
  15. ## set root "../.."
  16. ## set partname "xc7z020clg400-1"
  17. ## set hdl_files [list \
  18. ## $root/accelerator/hdl \
  19. ## $root/common/hdl/ \
  20. ## $root/emesh/hdl \
  21. ## $root/emmu/hdl \
  22. ## $root/axi/hdl \
  23. ## $root/emailbox/hdl \
  24. ## $root/edma/hdl \
  25. ## $root/elink/hdl \
  26. ## ]
  27. ## set ip_files []
  28. ## set constraints_files []
  29. # source ../../common/fpga/create_ip.tcl
  30. ## create_project -force $design $projdir -part $partname
  31. ## set_property target_language Verilog [current_project]
  32. ## set_property source_mgmt_mode None [current_project]
  33. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  34. ## create_fileset -srcset sources_1
  35. ## }
  36. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  37. ## set_property top $design [get_filesets sources_1]
  38. ## if {[string equal [get_filesets -quiet constraints_1] ""]} {
  39. ## create_fileset -constrset constraints_1
  40. ## }
  41. ## if {[llength $constraints_files] != 0} {
  42. ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
  43. ## }
  44. ## if {[llength $ip_files] != 0} {
  45. ##
  46. ## #Add to fileset
  47. ## add_files -norecurse -fileset [get_filesets sources_1] $ip_files
  48. ##
  49. ## #Set mode for IP
  50. ## foreach file $ip_files {
  51. ## #TODO: is this needed?
  52. ## set file_obj [get_files -of_objects [get_filesets sources_1] $file]
  53. ## set_property "synth_checkpoint_mode" "Singular" $file_obj
  54. ## }
  55. ## #RERUN/UPGRADE IP
  56. ## upgrade_ip [get_ips]
  57. ## }
  58. ## ipx::package_project -import_files -force -root_dir $projdir
  59. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockgate.v'.
  60. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_abs.v'.
  61. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isohi.v'.
  62. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_iddr.v'.
  63. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_datagate.v'.
  64. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_delay.v'.
  65. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isolo.v'.
  66. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux2.v'.
  67. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux12.v'.
  68. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc.v'.
  69. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux8.v'.
  70. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_add.v'.
  71. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_shifter.v'.
  72. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux.v'.
  73. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_decode.v'.
  74. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_encode.v'.
  75. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa92.v'.
  76. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_buf.v'.
  77. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat0.v'.
  78. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa62.v'.
  79. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_tristate.v'.
  80. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pulse2pulse.v'.
  81. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockdiv.v'.
  82. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/cfg_generic.v'.
  83. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_64b.v'.
  84. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_stretcher.v'.
  85. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_gray2bin.v'.
  86. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_ser2par.v'.
  87. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rsync.v'.
  88. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_counter.v'.
  89. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa42.v'.
  90. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg0.v'.
  91. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edge2pulse.v'.
  92. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux4.v'.
  93. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bitreverse.v'.
  94. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_8b.v'.
  95. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pll.v'.
  96. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg1.v'.
  97. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_oddr.v'.
  98. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_standby.v'.
  99. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_async.v'.
  100. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2gray.v'.
  101. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux6.v'.
  102. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_par2ser.v'.
  103. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rise2pulse.v'.
  104. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fall2pulse.v'.
  105. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_cdc.v'.
  106. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat1.v'.
  107. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_debouncer.v'.
  108. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux9.v'.
  109. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2onehot.v'.
  110. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockmux.v'.
  111. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgedetect.v'.
  112. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_7seg_decode.v'.
  113. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_parity.v'.
  114. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_memory_sp.v'.
  115. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_generic.v'.
  116. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa32.v'.
  117. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockor.v'.
  118. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux5.v'.
  119. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux7.v'.
  120. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_gate.v'.
  121. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux3.v'.
  122. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_buffer.v'.
  123. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgealign.v'.
  124. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_constants.v'.
  125. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_rdalign.v'.
  126. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/ememory.v'.
  127. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_wralign.v'.
  128. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_if.v'.
  129. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_readback.v'.
  130. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emmu/hdl/emmu.v'.
  131. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox_regmap.vh'.
  132. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox.v'.
  133. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_dp.v'.
  134. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regs.v'.
  135. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma.v'.
  136. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_ctrl.v'.
  137. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regmap.vh'.
  138. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx.v'.
  139. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_arbiter.v'.
  140. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/ecfg_if.v'.
  141. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/axi_elink.v'.
  142. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_core.v'.
  143. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_clocks.v'.
  144. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_clocks.v'.
  145. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_constants.vh'.
  146. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_protocol.v'.
  147. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_cfg.v'.
  148. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_io.v'.
  149. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_regmap.vh'.
  150. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx.v'.
  151. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_fifo.v'.
  152. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_remap.v'.
  153. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_remap.v'.
  154. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_arbiter.v'.
  155. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_core.v'.
  156. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_fifo.v'.
  157. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_io.v'.
  158. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink.v'.
  159. INFO: [Common 17-14] Message 'IP_Flow 19-3833' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  160. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
  161. INFO: [IP_Flow 19-234] Refreshing IP repositories
  162. INFO: [IP_Flow 19-1704] No user IP repositories specified
  163. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
  164. CRITICAL WARNING: [HDL 9-870] Macro <CFG_ASIC> is not defined. [src/oh_memory_dp.v:36]
  165. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_memory_dp.v:36]
  166. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_dsync.v:18]
  167. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/accelerator_regmap.vh" from the top-level HDL file.
  168. INFO: [IP_Flow 19-2228] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0'.
  169. INFO: [IP_Flow 19-2228] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0'.
  170. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
  171. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  172. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'.
  173. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  174. INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'irq' as interface 'irq'.
  175. INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
  176. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'sys_clk' as interface 'sys_clk'.
  177. INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((2 * spirit:decode(id('MODELPARAM_VALUE.AW'))) + 40)" into user parameter "PW".
  178. ## ipx::remove_memory_map {s_axi} [ipx::current_core]
  179. ## ipx::add_memory_map {s_axi} [ipx::current_core]
  180. ## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
  181. INFO: [IP_Flow 19-4728] Bus Interface 'sys_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
  182. ## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
  183. WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead
  184. ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
  185. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  186. ## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
  187. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  188. WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead
  189. ## set_property range {65536} [ipx::get_address_block axi_lite \
  190. ## [ipx::get_memory_map s_axi [ipx::current_core]]]
  191. ## set_property vendor {www.parallella.org} [ipx::current_core]
  192. ## set_property library {user} [ipx::current_core]
  193. ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
  194. ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core]
  195. ## set_property company_url {www.parallella.org} [ipx::current_core]
  196. ## set_property supported_families { \
  197. ## {virtex7} {Production} \
  198. ## {qvirtex7} {Production} \
  199. ## {kintex7} {Production} \
  200. ## {kintex7l} {Production} \
  201. ## {qkintex7} {Production} \
  202. ## {qkintex7l} {Production} \
  203. ## {artix7} {Production} \
  204. ## {artix7l} {Production} \
  205. ## {aartix7} {Production} \
  206. ## {qartix7} {Production} \
  207. ## {zynq} {Production} \
  208. ## {qzynq} {Production} \
  209. ## {azynq} {Production} \
  210. ## } [ipx::current_core]
  211. WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files.
  212. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files.
  213. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7. Please verify spelling and reissue command to set the supported files.
  214. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7l. Please verify spelling and reissue command to set the supported files.
  215. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files.
  216. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files.
  217. WARNING: [IP_Flow 19-4623] Unrecognized family artix7. Please verify spelling and reissue command to set the supported files.
  218. WARNING: [IP_Flow 19-4623] Unrecognized family artix7l. Please verify spelling and reissue command to set the supported files.
  219. WARNING: [IP_Flow 19-4623] Unrecognized family aartix7. Please verify spelling and reissue command to set the supported files.
  220. WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files.
  221. ## ipx::archive_core [concat $design.zip] [ipx::current_core]
  222. ## exit
  223. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:11:58 2017...
  225. ****** Vivado v2016.2 (64-bit)
  226. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  227. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  228. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  230. source run.tcl
  231. # source ./run_params.tcl
  232. ## set design system
  233. ## set projdir ./
  234. ## set partname "xc7z020clg400-1"
  235. ## set ip_repos [list "."]
  236. ## set hdl_files []
  237. ## set constraints_files []
  238. # source ../../common/fpga/system_init.tcl
  239. ## create_project -force $design $projdir -part $partname
  240. ## set_property target_language Verilog [current_project]
  241. ## set report_dir $projdir/reports
  242. ## set results_dir $projdir/results
  243. ## if ![file exists $report_dir] {file mkdir $report_dir}
  244. ## if ![file exists $results_dir] {file mkdir $results_dir}
  245. ## set other_repos [get_property ip_repo_paths [current_project]]
  246. ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project]
  247. ## update_ip_catalog
  248. INFO: [IP_Flow 19-234] Refreshing IP repositories
  249. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga'.
  250. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
  251. ## create_bd_design "system"
  252. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  253. ## source $projdir/system_bd.tcl
  254. ### namespace eval _tcl {
  255. ### proc get_script_folder {} {
  256. ### set script_path [file normalize [info script]]
  257. ### set script_folder [file dirname $script_path]
  258. ### return $script_folder
  259. ### }
  260. ### }
  261. ### variable script_folder
  262. ### set script_folder [_tcl::get_script_folder]
  263. ### set scripts_vivado_version 2016.2
  264. ### set current_vivado_version [version -short]
  265. ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  266. ### puts ""
  267. ### catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
  268. ###
  269. ### return 1
  270. ### }
  271. ### set list_projs [get_projects -quiet]
  272. ### if { $list_projs eq "" } {
  273. ### create_project project_1 myproj -part xc7z020clg400-1
  274. ### }
  275. ### set design_name system
  276. ### set errMsg ""
  277. ### set nRet 0
  278. ### set cur_design [current_bd_design -quiet]
  279. ### set list_cells [get_bd_cells -quiet]
  280. ### if { ${design_name} eq "" } {
  281. ### # USE CASES:
  282. ### # 1) Design_name not set
  283. ###
  284. ### set errMsg "Please set the variable <design_name> to a non-empty value."
  285. ### set nRet 1
  286. ###
  287. ### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
  288. ### # USE CASES:
  289. ### # 2): Current design opened AND is empty AND names same.
  290. ### # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
  291. ### # 4): Current design opened AND is empty AND names diff; design_name exists in project.
  292. ###
  293. ### if { $cur_design ne $design_name } {
  294. ### common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
  295. ### set design_name [get_property NAME $cur_design]
  296. ### }
  297. ### common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
  298. ###
  299. ### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
  300. ### # USE CASES:
  301. ### # 5) Current design opened AND has components AND same names.
  302. ###
  303. ### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  304. ### set nRet 1
  305. ### } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
  306. ### # USE CASES:
  307. ### # 6) Current opened design, has components, but diff names, design_name exists in project.
  308. ### # 7) No opened design, design_name exists in project.
  309. ###
  310. ### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  311. ### set nRet 2
  312. ###
  313. ### } else {
  314. ### # USE CASES:
  315. ### # 8) No opened design, design_name not in project.
  316. ### # 9) Current opened design, has components, but diff names, design_name not in project.
  317. ###
  318. ### common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  319. ###
  320. ### create_bd_design $design_name
  321. ###
  322. ### common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
  323. ### current_bd_design $design_name
  324. ###
  325. ### }
  326. INFO: [BD_TCL-2] Constructing design in IPI design <system>...
  327. ### common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
  328. INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "system".
  329. ### if { $nRet != 0 } {
  330. ### catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
  331. ### return $nRet
  332. ### }
  333. ### proc create_root_design { parentCell } {
  334. ###
  335. ### variable script_folder
  336. ###
  337. ### if { $parentCell eq "" } {
  338. ### set parentCell [get_bd_cells /]
  339. ### }
  340. ###
  341. ### # Get object for parentCell
  342. ### set parentObj [get_bd_cells $parentCell]
  343. ### if { $parentObj == "" } {
  344. ### catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  345. ### return
  346. ### }
  347. ###
  348. ### # Make sure parentObj is hier blk
  349. ### set parentType [get_property TYPE $parentObj]
  350. ### if { $parentType ne "hier" } {
  351. ### catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  352. ### return
  353. ### }
  354. ###
  355. ### # Save current instance; Restore later
  356. ### set oldCurInst [current_bd_instance .]
  357. ###
  358. ### # Set parent object as current
  359. ### current_bd_instance $parentObj
  360. ###
  361. ###
  362. ### # Create interface ports
  363. ###
  364. ### # Create ports
  365. ###
  366. ### # Create port connections
  367. ###
  368. ### # Create address segments
  369. ###
  370. ###
  371. ### # Restore current instance
  372. ### current_bd_instance $oldCurInst
  373. ###
  374. ### save_bd_design
  375. ### }
  376. ### create_root_design ""
  377. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
  378. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  379. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  380. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  381. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  382. ## create_fileset -srcset sources_1
  383. ## }
  384. ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  385. ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper
  386. ## if {[llength $hdl_files] != 0} {
  387. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  388. ## }
  389. ## if {[string equal [get_filesets -quiet constrs_1] ""]} {
  390. ## create_fileset -constrset constrs_1
  391. ## }
  392. ## if {[llength $constraints_files] != 0} {
  393. ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files
  394. ## }
  395. # source ../../common/fpga/system_build.tcl
  396. ## validate_bd_design
  397. INFO: [BD 5-320] Validate design is not run, since the design is already validated.
  398. ## write_bd_tcl -force ./system_bd.tcl
  399. INFO: [BD 5-148] Tcl file written out </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system_bd.tcl>.
  401. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
  402. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  403. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  404. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  405. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  406. ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  407. ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  408. ## if {[info exists oh_synthesis_options]} {
  409. ## puts "INFO: Synthesis with following options: $oh_synthesis_options"
  410. ## set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]
  411. ## }
  412. ## launch_runs synth_1
  413. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  414. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  415. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  416. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  417. Exporting to file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system.hwh
  418. Generated Block Design Tcl file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
  419. Generated Hardware Definition File /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.hwdef
  420. [Tue Jan 3 15:12:07 2017] Launched synth_1...
  421. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/runme.log
  422. ## wait_on_run synth_1
  423. [Tue Jan 3 15:12:07 2017] Waiting for synth_1 to finish...
  425. *** Running vivado
  426. with args -log system_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
  429. ****** Vivado v2016.2 (64-bit)
  430. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  431. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  432. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  434. source system_wrapper.tcl -notrace
  435. Command: synth_design -top system_wrapper -part xc7z020clg400-1
  436. Starting synth_design
  437. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
  438. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
  439. INFO: Launching helper process for spawning children vivado processes
  440. INFO: Helper process launched with PID 32612
  441. ---------------------------------------------------------------------------------
  442. Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1006.043 ; gain = 124.121 ; free physical = 136 ; free virtual = 3622
  443. ---------------------------------------------------------------------------------
  444. INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  445. INFO: [Synth 8-638] synthesizing module 'system' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
  446. INFO: [Synth 8-256] done synthesizing module 'system' (1#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
  447. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  448. INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  449. ---------------------------------------------------------------------------------
  450. Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
  451. ---------------------------------------------------------------------------------
  453. Report Check Netlist:
  454. +------+------------------+-------+---------+-------+------------------+
  455. | |Item |Errors |Warnings |Status |Description |
  456. +------+------------------+-------+---------+-------+------------------+
  457. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  458. +------+------------------+-------+---------+-------+------------------+
  459. ---------------------------------------------------------------------------------
  460. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
  461. ---------------------------------------------------------------------------------
  462. WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  463. INFO: [Device 21-403] Loading part xc7z020clg400-1
  464. INFO: [Project 1-570] Preparing netlist for logic optimization
  466. Processing XDC Constraints
  467. Initializing timing engine
  468. Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
  469. Finished Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
  470. Completed Processing XDC Constraints
  472. INFO: [Project 1-111] Unisim Transformation Summary:
  473. No Unisim elements were transformed.
  475. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1337.918 ; gain = 0.000 ; free physical = 142 ; free virtual = 3432
  476. ---------------------------------------------------------------------------------
  477. Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  478. ---------------------------------------------------------------------------------
  479. ---------------------------------------------------------------------------------
  480. Start Loading Part and Timing Information
  481. ---------------------------------------------------------------------------------
  482. Loading part: xc7z020clg400-1
  483. ---------------------------------------------------------------------------------
  484. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  485. ---------------------------------------------------------------------------------
  486. ---------------------------------------------------------------------------------
  487. Start Applying 'set_property' XDC Constraints
  488. ---------------------------------------------------------------------------------
  489. Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ).
  490. ---------------------------------------------------------------------------------
  491. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  492. ---------------------------------------------------------------------------------
  493. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  494. ---------------------------------------------------------------------------------
  495. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  496. ---------------------------------------------------------------------------------
  498. Report RTL Partitions:
  499. +-+--------------+------------+----------+
  500. | |RTL Partition |Replication |Instances |
  501. +-+--------------+------------+----------+
  502. +-+--------------+------------+----------+
  503. ---------------------------------------------------------------------------------
  504. Start RTL Component Statistics
  505. ---------------------------------------------------------------------------------
  506. Detailed RTL Component Info :
  507. ---------------------------------------------------------------------------------
  508. Finished RTL Component Statistics
  509. ---------------------------------------------------------------------------------
  510. ---------------------------------------------------------------------------------
  511. Start RTL Hierarchical Component Statistics
  512. ---------------------------------------------------------------------------------
  513. Hierarchical RTL Component report
  514. ---------------------------------------------------------------------------------
  515. Finished RTL Hierarchical Component Statistics
  516. ---------------------------------------------------------------------------------
  517. ---------------------------------------------------------------------------------
  518. Start Part Resource Summary
  519. ---------------------------------------------------------------------------------
  520. Part Resources:
  521. DSPs: 220 (col length:60)
  522. BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
  523. ---------------------------------------------------------------------------------
  524. Finished Part Resource Summary
  525. ---------------------------------------------------------------------------------
  526. Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  527. ---------------------------------------------------------------------------------
  528. Start Cross Boundary Optimization
  529. ---------------------------------------------------------------------------------
  530. ---------------------------------------------------------------------------------
  531. Finished Cross Boundary Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  532. ---------------------------------------------------------------------------------
  533. Finished Parallel Reinference : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  535. Report RTL Partitions:
  536. +-+--------------+------------+----------+
  537. | |RTL Partition |Replication |Instances |
  538. +-+--------------+------------+----------+
  539. +-+--------------+------------+----------+
  540. ---------------------------------------------------------------------------------
  541. Start Area Optimization
  542. ---------------------------------------------------------------------------------
  543. ---------------------------------------------------------------------------------
  544. Finished Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423
  545. ---------------------------------------------------------------------------------
  546. Finished Parallel Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423
  548. Report RTL Partitions:
  549. +-+--------------+------------+----------+
  550. | |RTL Partition |Replication |Instances |
  551. +-+--------------+------------+----------+
  552. +-+--------------+------------+----------+
  553. ---------------------------------------------------------------------------------
  554. Start Timing Optimization
  555. ---------------------------------------------------------------------------------
  556. ---------------------------------------------------------------------------------
  557. Start Applying XDC Timing Constraints
  558. ---------------------------------------------------------------------------------
  559. ---------------------------------------------------------------------------------
  560. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
  561. ---------------------------------------------------------------------------------
  562. ---------------------------------------------------------------------------------
  563. Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
  564. ---------------------------------------------------------------------------------
  566. Report RTL Partitions:
  567. +-+--------------+------------+----------+
  568. | |RTL Partition |Replication |Instances |
  569. +-+--------------+------------+----------+
  570. +-+--------------+------------+----------+
  571. ---------------------------------------------------------------------------------
  572. Start Technology Mapping
  573. ---------------------------------------------------------------------------------
  574. ---------------------------------------------------------------------------------
  575. Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  576. ---------------------------------------------------------------------------------
  577. Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  579. Report RTL Partitions:
  580. +-+--------------+------------+----------+
  581. | |RTL Partition |Replication |Instances |
  582. +-+--------------+------------+----------+
  583. +-+--------------+------------+----------+
  584. Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  585. ---------------------------------------------------------------------------------
  586. Start IO Insertion
  587. ---------------------------------------------------------------------------------
  588. ---------------------------------------------------------------------------------
  589. Start Flattening Before IO Insertion
  590. ---------------------------------------------------------------------------------
  591. ---------------------------------------------------------------------------------
  592. Finished Flattening Before IO Insertion
  593. ---------------------------------------------------------------------------------
  594. ---------------------------------------------------------------------------------
  595. Start Final Netlist Cleanup
  596. ---------------------------------------------------------------------------------
  597. ---------------------------------------------------------------------------------
  598. Finished Final Netlist Cleanup
  599. ---------------------------------------------------------------------------------
  600. ---------------------------------------------------------------------------------
  601. Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  602. ---------------------------------------------------------------------------------
  604. Report Check Netlist:
  605. +------+------------------+-------+---------+-------+------------------+
  606. | |Item |Errors |Warnings |Status |Description |
  607. +------+------------------+-------+---------+-------+------------------+
  608. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  609. +------+------------------+-------+---------+-------+------------------+
  610. ---------------------------------------------------------------------------------
  611. Start Renaming Generated Instances
  612. ---------------------------------------------------------------------------------
  613. ---------------------------------------------------------------------------------
  614. Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  615. ---------------------------------------------------------------------------------
  617. Report RTL Partitions:
  618. +-+--------------+------------+----------+
  619. | |RTL Partition |Replication |Instances |
  620. +-+--------------+------------+----------+
  621. +-+--------------+------------+----------+
  622. ---------------------------------------------------------------------------------
  623. Start Rebuilding User Hierarchy
  624. ---------------------------------------------------------------------------------
  625. ---------------------------------------------------------------------------------
  626. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  627. ---------------------------------------------------------------------------------
  628. ---------------------------------------------------------------------------------
  629. Start Renaming Generated Ports
  630. ---------------------------------------------------------------------------------
  631. ---------------------------------------------------------------------------------
  632. Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  633. ---------------------------------------------------------------------------------
  634. ---------------------------------------------------------------------------------
  635. Start Handling Custom Attributes
  636. ---------------------------------------------------------------------------------
  637. ---------------------------------------------------------------------------------
  638. Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  639. ---------------------------------------------------------------------------------
  640. ---------------------------------------------------------------------------------
  641. Start Renaming Generated Nets
  642. ---------------------------------------------------------------------------------
  643. ---------------------------------------------------------------------------------
  644. Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  645. ---------------------------------------------------------------------------------
  646. ---------------------------------------------------------------------------------
  647. Start Writing Synthesis Report
  648. ---------------------------------------------------------------------------------
  650. Report BlackBoxes:
  651. +------+--------------+----------+
  652. | |BlackBox name |Instances |
  653. +------+--------------+----------+
  654. |1 |system | 1|
  655. +------+--------------+----------+
  657. Report Cell Usage:
  658. +------+-------+------+
  659. | |Cell |Count |
  660. +------+-------+------+
  661. |1 |system | 1|
  662. +------+-------+------+
  664. Report Instance Areas:
  665. +------+---------+-------+------+
  666. | |Instance |Module |Cells |
  667. +------+---------+-------+------+
  668. |1 |top | | 0|
  669. +------+---------+-------+------+
  670. ---------------------------------------------------------------------------------
  671. Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  672. ---------------------------------------------------------------------------------
  673. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
  674. Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1363.918 ; gain = 104.434 ; free physical = 131 ; free virtual = 3377
  675. Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.926 ; gain = 482.004 ; free physical = 131 ; free virtual = 3377
  676. INFO: [Project 1-571] Translating synthesized netlist
  677. INFO: [Project 1-570] Preparing netlist for logic optimization
  678. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  679. INFO: [Project 1-111] Unisim Transformation Summary:
  680. No Unisim elements were transformed.
  682. INFO: [Common 17-83] Releasing license: Synthesis
  683. 13 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  684. synth_design completed successfully
  685. synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1364.918 ; gain = 410.457 ; free physical = 130 ; free virtual = 3377
  686. report_utilization: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1372.922 ; gain = 0.000 ; free physical = 129 ; free virtual = 3377
  687. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:31 2017...
  688. [Tue Jan 3 15:12:34 2017] synth_1 finished
  689. wait_on_run: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:27 . Memory (MB): peak = 1070.695 ; gain = 8.000 ; free physical = 619 ; free virtual = 3868
  690. ## launch_runs impl_1
  691. [Tue Jan 3 15:12:34 2017] Launched impl_1...
  692. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
  693. ## wait_on_run impl_1
  694. [Tue Jan 3 15:12:34 2017] Waiting for impl_1 to finish...
  696. *** Running vivado
  697. with args -log system_wrapper.vdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
  700. ****** Vivado v2016.2 (64-bit)
  701. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  702. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  703. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  705. source system_wrapper.tcl -notrace
  706. Design is defaulting to srcset: sources_1
  707. Design is defaulting to constrset: constrs_1
  708. INFO: [Project 1-479] Netlist was created with Vivado 2016.2
  709. INFO: [Device 21-403] Loading part xc7z020clg400-1
  710. INFO: [Project 1-570] Preparing netlist for logic optimization
  711. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  712. CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  713. INFO: [Project 1-111] Unisim Transformation Summary:
  714. No Unisim elements were transformed.
  716. Command: opt_design
  717. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  718. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  719. Running DRC as a precondition to command opt_design
  721. Starting DRC Task
  722. INFO: [DRC 23-27] Running DRC with 8 threads
  723. ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
  724. INFO: [Project 1-461] DRC finished with 1 Errors
  725. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  726. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
  728. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1280.484 ; gain = 66.031 ; free physical = 222 ; free virtual = 3489
  729. INFO: [Common 17-83] Releasing license: Implementation
  730. 10 Infos, 0 Warnings, 1 Critical Warnings and 2 Errors encountered.
  731. opt_design failed
  732. ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
  734. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:44 2017...
  735. [Tue Jan 3 15:12:46 2017] impl_1 finished
  736. wait_on_run: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:12 . Memory (MB): peak = 1070.695 ; gain = 0.000 ; free physical = 597 ; free virtual = 3865
  737. ## launch_runs impl_1 -to_step write_bitstream
  738. [Tue Jan 3 15:12:46 2017] Launched impl_1...
  739. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
  740. ## wait_on_run impl_1
  741. [Tue Jan 3 15:12:46 2017] Waiting for impl_1 to finish...
  742. [Tue Jan 3 15:12:46 2017] impl_1 finished
  743. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:46 2017...
  744. [ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit
  745. cp: cannot stat 'system_wrapper.bit.bin': No such file or directory
  746. [promach@localhost fpga]$