1. [promach@localhost hello]$ ls
  2. hello.bin hello.dis hello.o Makefile sim.vcd
  3. hello.c hello.elf hello.vmem sim.gtkw stdout.000
  4. [promach@localhost hello]$ $OPTIMSOC/examples/sim/compute_tile/compute_tile_sim_singlecore --meminit=hello.vmem
  5. TOP.tb_compute_tile.u_compute_tile.gen_cores[0].u_core.u_cpu.bus_gen.ibus_bridge: Wishbone bus IF is B3_REGISTERED_FEEDBACK
  6. TOP.tb_compute_tile.u_compute_tile.gen_cores[0].u_core.u_cpu.bus_gen.dbus_bridge: Wishbone bus IF is B3_REGISTERED_FEEDBACK
  7. [ 22, 0] Software reset
  8. [ 8880, 0] Terminated at address 0x0000e8c0 (status: 1309)
  9. - ../src/optimsoc_trace_monitor_trace_monitor/verilog/trace_monitor.sv:89: Verilog $finish
  10. [promach@localhost hello]$ ls
  11. hello.bin hello.dis hello.o Makefile sim.vcd
  12. hello.c hello.elf hello.vmem sim.gtkw stdout.000
  13. [phung@localhost hello]$ cat stdout.000
  14. # OpTiMSoC trace_monitor stdout file
  15. # [TIME, CORE] MESSAGE
  16. [promach@localhost hello]$