- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity key_expansion is
- port
- (
- CLK : in std_logic;
- key_load: in std_logic;
- key : in std_logic_vector(127 downto 0);
- xkey0 : out std_logic_vector(31 downto 0);
- xkey1 : out std_logic_vector(31 downto 0);
- xkey2 : out std_logic_vector(31 downto 0);
- xkey3 : out std_logic_vector(31 downto 0)
- );
- attribute SIGIS : string;
- attribute SIGIS of CLK : signal is "Clk";
- end key_expansion;
- architecture EXAMPLE of key_expansion is
- component subbytes
- port(sbox_in : in std_logic_vector (7 downto 0);
- sbox_out : out std_logic_vector (7 downto 0) );
- end component;
- component round_constant
- port(CLK, key_load : in std_logic;
- rcon : std_logic_vector(31 downto 0));
- end component;
- -- signal rcon : std_logic_vector(8 downto 0);
- signal rcon, subword, tmp_w, w0, w1, w2, w3 : STD_LOGIC_VECTOR(31 downto 0) := (OTHERS => '0');
- --type rcon is array
- -- (integer range 0 to 0, integer range 0 to 9) of std_logic_vector(7 downto 0);
- --constant rcon := ( x"01" , x"02" , x"04" , x"08" , x"10" , x"20" , x"40" , x"80" , x"1b" , x"36" );
- begin
- s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out => subword(31 downto 24) );
- s1: subbytes port map ( sbox_in => tmp_w(15 downto 8) , sbox_out => subword(23 downto 16) );
- s2: subbytes port map ( sbox_in => tmp_w( 7 downto 0) , sbox_out => subword(15 downto 8) );
- s3: subbytes port map ( sbox_in => tmp_w(31 downto 24) , sbox_out => subword( 7 downto 0) );
- r0: round_constant port map (CLK => CLK, key_load => key_load, rcon => rcon );
- tmp_w <= w3;
- xkey0 <= w0;
- xkey1 <= w1;
- xkey2 <= w2;
- xkey3 <= w3;
- w_0:PROCESS(CLK) -- round key generation
- BEGIN
- if rising_edge(CLK) then -- Rising clock edge
- if key_load = '1' then
- w0 <= key(127 downto 96);
- w1 <= key( 95 downto 64);
- w2 <= key( 63 downto 32);
- w3 <= key( 31 downto 0);
- else
- w0 <= w0 xor subword xor rcon;
- w1 <= w0 xor w1 xor subword xor rcon;
- w2 <= w0 xor w2 xor w1 xor subword xor rcon;
- w3 <= w0 xor w3 xor w2 xor w1 xor subword xor rcon;
- end if;
- end if;
- END process w_0;
- end architecture EXAMPLE;