1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity key_expansion is
  5. port
  6. (
  7. CLK : in std_logic;
  8. key_load: in std_logic;
  9. key : in std_logic_vector(127 downto 0);
  10. xkey0 : out std_logic_vector(31 downto 0);
  11. xkey1 : out std_logic_vector(31 downto 0);
  12. xkey2 : out std_logic_vector(31 downto 0);
  13. xkey3 : out std_logic_vector(31 downto 0)
  14. );
  15. attribute SIGIS : string;
  16. attribute SIGIS of CLK : signal is "Clk";
  17. end key_expansion;
  18. architecture EXAMPLE of key_expansion is
  19. component subbytes
  20. port(sbox_in : in std_logic_vector (7 downto 0);
  21. sbox_out : out std_logic_vector (7 downto 0) );
  22. end component;
  23. component round_constant
  24. port(CLK, key_load : in std_logic;
  25. rcon : std_logic_vector(31 downto 0));
  26. end component;
  27. -- signal rcon : std_logic_vector(8 downto 0);
  28. signal rcon, subword, tmp_w, w0, w1, w2, w3 : STD_LOGIC_VECTOR(31 downto 0) := (OTHERS => '0');
  29. --type rcon is array
  30. -- (integer range 0 to 0, integer range 0 to 9) of std_logic_vector(7 downto 0);
  31. --constant rcon := ( x"01" , x"02" , x"04" , x"08" , x"10" , x"20" , x"40" , x"80" , x"1b" , x"36" );
  32. begin
  33. s0: subbytes port map ( sbox_in => tmp_w(23 downto 16) , sbox_out => subword(31 downto 24) );
  34. s1: subbytes port map ( sbox_in => tmp_w(15 downto 8) , sbox_out => subword(23 downto 16) );
  35. s2: subbytes port map ( sbox_in => tmp_w( 7 downto 0) , sbox_out => subword(15 downto 8) );
  36. s3: subbytes port map ( sbox_in => tmp_w(31 downto 24) , sbox_out => subword( 7 downto 0) );
  37. r0: round_constant port map (CLK => CLK, key_load => key_load, rcon => rcon );
  38. tmp_w <= w3;
  39. xkey0 <= w0;
  40. xkey1 <= w1;
  41. xkey2 <= w2;
  42. xkey3 <= w3;
  43. w_0:PROCESS(CLK) -- round key generation
  44. BEGIN
  45. if rising_edge(CLK) then -- Rising clock edge
  46. if key_load = '1' then
  47. w0 <= key(127 downto 96);
  48. w1 <= key( 95 downto 64);
  49. w2 <= key( 63 downto 32);
  50. w3 <= key( 31 downto 0);
  51. else
  52. w0 <= w0 xor subword xor rcon;
  53. w1 <= w0 xor w1 xor subword xor rcon;
  54. w2 <= w0 xor w2 xor w1 xor subword xor rcon;
  55. w3 <= w0 xor w3 xor w2 xor w1 xor subword xor rcon;
  56. end if;
  57. end if;
  58. END process w_0;
  59. end architecture EXAMPLE;