1. /************************************************
  2. The Verilog HDL code example is from the book
  3. Computer Principles and Design in Verilog HDL
  4. by Yamin Li, published by A JOHN WILEY & SONS
  5. ************************************************/
  6. module div_restoring (a,b,start,clk,clrn,q,r,busy,ready,count);
  7. input [31:0] a; // dividend
  8. input [15:0] b; // divisor
  9. input start; // start
  10. input clk, clrn; // clk,reset
  11. output [31:0] q; // quotient
  12. output [15:0] r; // remainder
  13. output reg busy; // busy
  14. output reg ready; // ready
  15. output [4:0] count; // counter
  16. reg [31:0] reg_q;
  17. reg [15:0] reg_r;
  18. reg [15:0] reg_b;
  19. reg [4:0] count;
  20. wire [16:0] sub_out = {reg_r,reg_q[31]} - {1'b0,reg_b}; // sub
  21. wire [15:0] mux_out = sub_out[16]? // restoring
  22. {reg_r[14:0],reg_q[31]} : sub_out[15:0]; // or not
  23. assign q = reg_q;
  24. assign r = reg_r;
  25. always @ (posedge clk or negedge clrn) begin
  26. if (!clrn) begin
  27. busy <= 0;
  28. ready <= 0;
  29. end else begin
  30. if (start) begin
  31. reg_q <= a; // load a
  32. reg_b <= b; // load b
  33. reg_r <= 0;
  34. busy <= 1;
  35. ready <= 0;
  36. count <= 0;
  37. end else if (busy) begin
  38. reg_q <= {reg_q[30:0],~sub_out[16]}; // << 1
  39. reg_r <= mux_out;
  40. count <= count + 5'b1; // counter++
  41. if (count == 5'h1f) begin // finished
  42. busy <= 0;
  43. ready <= 1; // q,r ready
  44. end
  45. end
  46. end
  47. end
  48. endmodule

div_restoring.v