1. [[email protected] oh]$ cd src/accelerator/fpga/
  2. [[email protected] fpga]$ ./build.sh
  3. rm: cannot remove 'system_wrapper.bit.bin': No such file or directory
  4. rm: cannot remove 'bit2bin.bin': No such file or directory
  5. ****** Vivado v2016.2 (64-bit)
  6. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  7. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  8. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  9. source package.tcl
  10. # source ./ip_params.tcl
  11. ## set design axi_accelerator
  12. ## set projdir ./
  13. ## set root "../.."
  14. ## set partname "xc7z020clg400-1"
  15. ## set hdl_files [list \
  16. ## $root/accelerator/hdl \
  17. ## $root/common/hdl/ \
  18. ## $root/emesh/hdl \
  19. ## $root/emmu/hdl \
  20. ## $root/axi/hdl \
  21. ## $root/emailbox/hdl \
  22. ## $root/edma/hdl \
  23. ## $root/elink/hdl \
  24. ## ]
  25. ## set ip_files []
  26. ## set constraints_files []
  27. # source ../../common/fpga/create_ip.tcl
  28. ## create_project -force $design $projdir -part $partname
  29. ## set_property target_language Verilog [current_project]
  30. ## set_property source_mgmt_mode None [current_project]
  31. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  32. ## create_fileset -srcset sources_1
  33. ## }
  34. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  35. ## set_property top $design [get_filesets sources_1]
  36. ## if {[string equal [get_filesets -quiet constraints_1] ""]} {
  37. ## create_fileset -constrset constraints_1
  38. ## }
  39. ## if {[llength $constraints_files] != 0} {
  40. ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
  41. ## }
  42. ## if {[llength $ip_files] != 0} {
  43. ##
  44. ## #Add to fileset
  45. ## add_files -norecurse -fileset [get_filesets sources_1] $ip_files
  46. ##
  47. ## #Set mode for IP
  48. ## foreach file $ip_files {
  49. ## #TODO: is this needed?
  50. ## set file_obj [get_files -of_objects [get_filesets sources_1] $file]
  51. ## set_property "synth_checkpoint_mode" "Singular" $file_obj
  52. ## }
  53. ## #RERUN/UPGRADE IP
  54. ## upgrade_ip [get_ips]
  55. ## }
  56. ## ipx::package_project -import_files -force -root_dir $projdir
  57. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockgate.v'.
  58. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_abs.v'.
  59. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isohi.v'.
  60. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_iddr.v'.
  61. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_datagate.v'.
  62. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_delay.v'.
  63. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_isolo.v'.
  64. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux2.v'.
  65. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux12.v'.
  66. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc.v'.
  67. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux8.v'.
  68. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_add.v'.
  69. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_shifter.v'.
  70. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux.v'.
  71. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_decode.v'.
  72. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_8b10b_encode.v'.
  73. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa92.v'.
  74. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_buf.v'.
  75. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat0.v'.
  76. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa62.v'.
  77. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_tristate.v'.
  78. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pulse2pulse.v'.
  79. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockdiv.v'.
  80. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/cfg_generic.v'.
  81. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_64b.v'.
  82. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_stretcher.v'.
  83. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_gray2bin.v'.
  84. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_ser2par.v'.
  85. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rsync.v'.
  86. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_counter.v'.
  87. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa42.v'.
  88. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg0.v'.
  89. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edge2pulse.v'.
  90. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux4.v'.
  91. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bitreverse.v'.
  92. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_crc32_8b.v'.
  93. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pll.v'.
  94. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_reg1.v'.
  95. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_oddr.v'.
  96. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_standby.v'.
  97. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_async.v'.
  98. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2gray.v'.
  99. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux6.v'.
  100. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_par2ser.v'.
  101. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_rise2pulse.v'.
  102. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fall2pulse.v'.
  103. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_cdc.v'.
  104. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_lat1.v'.
  105. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_debouncer.v'.
  106. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux9.v'.
  107. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_bin2onehot.v'.
  108. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockmux.v'.
  109. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgedetect.v'.
  110. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_7seg_decode.v'.
  111. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_parity.v'.
  112. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_memory_sp.v'.
  113. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_fifo_generic.v'.
  114. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_csa32.v'.
  115. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_clockor.v'.
  116. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux5.v'.
  117. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux7.v'.
  118. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_pwr_gate.v'.
  119. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_mux3.v'.
  120. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_buffer.v'.
  121. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/common/hdl/oh_edgealign.v'.
  122. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_constants.v'.
  123. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_rdalign.v'.
  124. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/ememory.v'.
  125. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_wralign.v'.
  126. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_if.v'.
  127. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emesh/hdl/emesh_readback.v'.
  128. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emmu/hdl/emmu.v'.
  129. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox_regmap.vh'.
  130. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/emailbox/hdl/emailbox.v'.
  131. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_dp.v'.
  132. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regs.v'.
  133. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma.v'.
  134. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_ctrl.v'.
  135. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/edma/hdl/edma_regmap.vh'.
  136. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx.v'.
  137. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_arbiter.v'.
  138. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/ecfg_if.v'.
  139. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/axi_elink.v'.
  140. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_core.v'.
  141. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_clocks.v'.
  142. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_clocks.v'.
  143. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_constants.vh'.
  144. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_protocol.v'.
  145. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_cfg.v'.
  146. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_io.v'.
  147. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink_regmap.vh'.
  148. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx.v'.
  149. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_fifo.v'.
  150. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_remap.v'.
  151. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_remap.v'.
  152. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_arbiter.v'.
  153. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_core.v'.
  154. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/erx_fifo.v'.
  155. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/etx_io.v'.
  156. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/elink/hdl/elink.v'.
  157. INFO: [Common 17-14] Message 'IP_Flow 19-3833' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  158. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
  159. INFO: [IP_Flow 19-234] Refreshing IP repositories
  160. INFO: [IP_Flow 19-1704] No user IP repositories specified
  161. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
  162. CRITICAL WARNING: [HDL 9-870] Macro <CFG_ASIC> is not defined. [src/oh_memory_dp.v:36]
  163. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_memory_dp.v:36]
  164. CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_dsync.v:18]
  165. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/accelerator_regmap.vh" from the top-level HDL file.
  166. INFO: [IP_Flow 19-2228] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0'.
  167. INFO: [IP_Flow 19-2228] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0'.
  168. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
  169. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  170. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'.
  171. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
  172. INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'irq' as interface 'irq'.
  173. INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
  174. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'sys_clk' as interface 'sys_clk'.
  175. INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((2 * spirit:decode(id('MODELPARAM_VALUE.AW'))) + 40)" into user parameter "PW".
  176. ## ipx::remove_memory_map {s_axi} [ipx::current_core]
  177. ## ipx::add_memory_map {s_axi} [ipx::current_core]
  178. ## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core]
  179. INFO: [IP_Flow 19-4728] Bus Interface 'sys_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
  180. ## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core]
  181. WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead
  182. ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
  183. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  184. ## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
  185. WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead
  186. WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead
  187. ## set_property range {65536} [ipx::get_address_block axi_lite \
  188. ## [ipx::get_memory_map s_axi [ipx::current_core]]]
  189. ## set_property vendor {www.parallella.org} [ipx::current_core]
  190. ## set_property library {user} [ipx::current_core]
  191. ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
  192. ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core]
  193. ## set_property company_url {www.parallella.org} [ipx::current_core]
  194. ## set_property supported_families { \
  195. ## {virtex7} {Production} \
  196. ## {qvirtex7} {Production} \
  197. ## {kintex7} {Production} \
  198. ## {kintex7l} {Production} \
  199. ## {qkintex7} {Production} \
  200. ## {qkintex7l} {Production} \
  201. ## {artix7} {Production} \
  202. ## {artix7l} {Production} \
  203. ## {aartix7} {Production} \
  204. ## {qartix7} {Production} \
  205. ## {zynq} {Production} \
  206. ## {qzynq} {Production} \
  207. ## {azynq} {Production} \
  208. ## } [ipx::current_core]
  209. WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files.
  210. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files.
  211. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7. Please verify spelling and reissue command to set the supported files.
  212. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7l. Please verify spelling and reissue command to set the supported files.
  213. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files.
  214. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files.
  215. WARNING: [IP_Flow 19-4623] Unrecognized family artix7. Please verify spelling and reissue command to set the supported files.
  216. WARNING: [IP_Flow 19-4623] Unrecognized family artix7l. Please verify spelling and reissue command to set the supported files.
  217. WARNING: [IP_Flow 19-4623] Unrecognized family aartix7. Please verify spelling and reissue command to set the supported files.
  218. WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files.
  219. ## ipx::archive_core [concat $design.zip] [ipx::current_core]
  220. ## exit
  221. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:11:58 2017...
  222. ****** Vivado v2016.2 (64-bit)
  223. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  224. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  225. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  226. source run.tcl
  227. # source ./run_params.tcl
  228. ## set design system
  229. ## set projdir ./
  230. ## set partname "xc7z020clg400-1"
  231. ## set ip_repos [list "."]
  232. ## set hdl_files []
  233. ## set constraints_files []
  234. # source ../../common/fpga/system_init.tcl
  235. ## create_project -force $design $projdir -part $partname
  236. ## set_property target_language Verilog [current_project]
  237. ## set report_dir $projdir/reports
  238. ## set results_dir $projdir/results
  239. ## if ![file exists $report_dir] {file mkdir $report_dir}
  240. ## if ![file exists $results_dir] {file mkdir $results_dir}
  241. ## set other_repos [get_property ip_repo_paths [current_project]]
  242. ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project]
  243. ## update_ip_catalog
  244. INFO: [IP_Flow 19-234] Refreshing IP repositories
  245. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga'.
  246. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
  247. ## create_bd_design "system"
  248. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  249. ## source $projdir/system_bd.tcl
  250. ### namespace eval _tcl {
  251. ### proc get_script_folder {} {
  252. ### set script_path [file normalize [info script]]
  253. ### set script_folder [file dirname $script_path]
  254. ### return $script_folder
  255. ### }
  256. ### }
  257. ### variable script_folder
  258. ### set script_folder [_tcl::get_script_folder]
  259. ### set scripts_vivado_version 2016.2
  260. ### set current_vivado_version [version -short]
  261. ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  262. ### puts ""
  263. ### catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
  264. ###
  265. ### return 1
  266. ### }
  267. ### set list_projs [get_projects -quiet]
  268. ### if { $list_projs eq "" } {
  269. ### create_project project_1 myproj -part xc7z020clg400-1
  270. ### }
  271. ### set design_name system
  272. ### set errMsg ""
  273. ### set nRet 0
  274. ### set cur_design [current_bd_design -quiet]
  275. ### set list_cells [get_bd_cells -quiet]
  276. ### if { ${design_name} eq "" } {
  277. ### # USE CASES:
  278. ### # 1) Design_name not set
  279. ###
  280. ### set errMsg "Please set the variable <design_name> to a non-empty value."
  281. ### set nRet 1
  282. ###
  283. ### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
  284. ### # USE CASES:
  285. ### # 2): Current design opened AND is empty AND names same.
  286. ### # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
  287. ### # 4): Current design opened AND is empty AND names diff; design_name exists in project.
  288. ###
  289. ### if { $cur_design ne $design_name } {
  290. ### common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
  291. ### set design_name [get_property NAME $cur_design]
  292. ### }
  293. ### common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
  294. ###
  295. ### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
  296. ### # USE CASES:
  297. ### # 5) Current design opened AND has components AND same names.
  298. ###
  299. ### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  300. ### set nRet 1
  301. ### } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
  302. ### # USE CASES:
  303. ### # 6) Current opened design, has components, but diff names, design_name exists in project.
  304. ### # 7) No opened design, design_name exists in project.
  305. ###
  306. ### set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
  307. ### set nRet 2
  308. ###
  309. ### } else {
  310. ### # USE CASES:
  311. ### # 8) No opened design, design_name not in project.
  312. ### # 9) Current opened design, has components, but diff names, design_name not in project.
  313. ###
  314. ### common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
  315. ###
  316. ### create_bd_design $design_name
  317. ###
  318. ### common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
  319. ### current_bd_design $design_name
  320. ###
  321. ### }
  322. INFO: [BD_TCL-2] Constructing design in IPI design <system>...
  323. ### common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
  324. INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "system".
  325. ### if { $nRet != 0 } {
  326. ### catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
  327. ### return $nRet
  328. ### }
  329. ### proc create_root_design { parentCell } {
  330. ###
  331. ### variable script_folder
  332. ###
  333. ### if { $parentCell eq "" } {
  334. ### set parentCell [get_bd_cells /]
  335. ### }
  336. ###
  337. ### # Get object for parentCell
  338. ### set parentObj [get_bd_cells $parentCell]
  339. ### if { $parentObj == "" } {
  340. ### catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
  341. ### return
  342. ### }
  343. ###
  344. ### # Make sure parentObj is hier blk
  345. ### set parentType [get_property TYPE $parentObj]
  346. ### if { $parentType ne "hier" } {
  347. ### catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
  348. ### return
  349. ### }
  350. ###
  351. ### # Save current instance; Restore later
  352. ### set oldCurInst [current_bd_instance .]
  353. ###
  354. ### # Set parent object as current
  355. ### current_bd_instance $parentObj
  356. ###
  357. ###
  358. ### # Create interface ports
  359. ###
  360. ### # Create ports
  361. ###
  362. ### # Create port connections
  363. ###
  364. ### # Create address segments
  365. ###
  366. ###
  367. ### # Restore current instance
  368. ### current_bd_instance $oldCurInst
  369. ###
  370. ### save_bd_design
  371. ### }
  372. ### create_root_design ""
  373. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
  374. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  375. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  376. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  377. ## if {[string equal [get_filesets -quiet sources_1] ""]} {
  378. ## create_fileset -srcset sources_1
  379. ## }
  380. ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  381. ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper
  382. ## if {[llength $hdl_files] != 0} {
  383. ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
  384. ## }
  385. ## if {[string equal [get_filesets -quiet constrs_1] ""]} {
  386. ## create_fileset -constrset constrs_1
  387. ## }
  388. ## if {[llength $constraints_files] != 0} {
  389. ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files
  390. ## }
  391. # source ../../common/fpga/system_build.tcl
  392. ## validate_bd_design
  393. INFO: [BD 5-320] Validate design is not run, since the design is already validated.
  394. ## write_bd_tcl -force ./system_bd.tcl
  395. INFO: [BD 5-148] Tcl file written out </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system_bd.tcl>.
  396. ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
  397. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  398. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  399. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  400. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  401. ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  402. ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
  403. ## if {[info exists oh_synthesis_options]} {
  404. ## puts "INFO: Synthesis with following options: $oh_synthesis_options"
  405. ## set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]
  406. ## }
  407. ## launch_runs synth_1
  408. INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
  409. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v
  410. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v
  411. Wrote : </home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/system.bd>
  412. Exporting to file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system.hwh
  413. Generated Block Design Tcl file /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
  414. Generated Hardware Definition File /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.hwdef
  415. [Tue Jan 3 15:12:07 2017] Launched synth_1...
  416. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/runme.log
  417. ## wait_on_run synth_1
  418. [Tue Jan 3 15:12:07 2017] Waiting for synth_1 to finish...
  419. *** Running vivado
  420. with args -log system_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
  421. ****** Vivado v2016.2 (64-bit)
  422. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  423. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  424. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  425. source system_wrapper.tcl -notrace
  426. Command: synth_design -top system_wrapper -part xc7z020clg400-1
  427. Starting synth_design
  428. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
  429. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
  430. INFO: Launching helper process for spawning children vivado processes
  431. INFO: Helper process launched with PID 32612
  432. ---------------------------------------------------------------------------------
  433. Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1006.043 ; gain = 124.121 ; free physical = 136 ; free virtual = 3622
  434. ---------------------------------------------------------------------------------
  435. INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  436. INFO: [Synth 8-638] synthesizing module 'system' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
  437. INFO: [Synth 8-256] done synthesizing module 'system' (1#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13]
  438. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  439. INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12]
  440. ---------------------------------------------------------------------------------
  441. Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
  442. ---------------------------------------------------------------------------------
  443. Report Check Netlist:
  444. +------+------------------+-------+---------+-------+------------------+
  445. | |Item |Errors |Warnings |Status |Description |
  446. +------+------------------+-------+---------+-------+------------------+
  447. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  448. +------+------------------+-------+---------+-------+------------------+
  449. ---------------------------------------------------------------------------------
  450. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1045.480 ; gain = 163.559 ; free physical = 124 ; free virtual = 3582
  451. ---------------------------------------------------------------------------------
  452. WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  453. INFO: [Device 21-403] Loading part xc7z020clg400-1
  454. INFO: [Project 1-570] Preparing netlist for logic optimization
  455. Processing XDC Constraints
  456. Initializing timing engine
  457. Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
  458. Finished Parsing XDC File [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc]
  459. Completed Processing XDC Constraints
  460. INFO: [Project 1-111] Unisim Transformation Summary:
  461. No Unisim elements were transformed.
  462. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1337.918 ; gain = 0.000 ; free physical = 142 ; free virtual = 3432
  463. ---------------------------------------------------------------------------------
  464. Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  465. ---------------------------------------------------------------------------------
  466. ---------------------------------------------------------------------------------
  467. Start Loading Part and Timing Information
  468. ---------------------------------------------------------------------------------
  469. Loading part: xc7z020clg400-1
  470. ---------------------------------------------------------------------------------
  471. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  472. ---------------------------------------------------------------------------------
  473. ---------------------------------------------------------------------------------
  474. Start Applying 'set_property' XDC Constraints
  475. ---------------------------------------------------------------------------------
  476. Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ).
  477. ---------------------------------------------------------------------------------
  478. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  479. ---------------------------------------------------------------------------------
  480. WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins
  481. ---------------------------------------------------------------------------------
  482. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 141 ; free virtual = 3431
  483. ---------------------------------------------------------------------------------
  484. Report RTL Partitions:
  485. +-+--------------+------------+----------+
  486. | |RTL Partition |Replication |Instances |
  487. +-+--------------+------------+----------+
  488. +-+--------------+------------+----------+
  489. ---------------------------------------------------------------------------------
  490. Start RTL Component Statistics
  491. ---------------------------------------------------------------------------------
  492. Detailed RTL Component Info :
  493. ---------------------------------------------------------------------------------
  494. Finished RTL Component Statistics
  495. ---------------------------------------------------------------------------------
  496. ---------------------------------------------------------------------------------
  497. Start RTL Hierarchical Component Statistics
  498. ---------------------------------------------------------------------------------
  499. Hierarchical RTL Component report
  500. ---------------------------------------------------------------------------------
  501. Finished RTL Hierarchical Component Statistics
  502. ---------------------------------------------------------------------------------
  503. ---------------------------------------------------------------------------------
  504. Start Part Resource Summary
  505. ---------------------------------------------------------------------------------
  506. Part Resources:
  507. DSPs: 220 (col length:60)
  508. BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
  509. ---------------------------------------------------------------------------------
  510. Finished Part Resource Summary
  511. ---------------------------------------------------------------------------------
  512. Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  513. ---------------------------------------------------------------------------------
  514. Start Cross Boundary Optimization
  515. ---------------------------------------------------------------------------------
  516. ---------------------------------------------------------------------------------
  517. Finished Cross Boundary Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  518. ---------------------------------------------------------------------------------
  519. Finished Parallel Reinference : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 139 ; free virtual = 3431
  520. Report RTL Partitions:
  521. +-+--------------+------------+----------+
  522. | |RTL Partition |Replication |Instances |
  523. +-+--------------+------------+----------+
  524. +-+--------------+------------+----------+
  525. ---------------------------------------------------------------------------------
  526. Start Area Optimization
  527. ---------------------------------------------------------------------------------
  528. ---------------------------------------------------------------------------------
  529. Finished Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423
  530. ---------------------------------------------------------------------------------
  531. Finished Parallel Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1337.918 ; gain = 455.996 ; free physical = 131 ; free virtual = 3423
  532. Report RTL Partitions:
  533. +-+--------------+------------+----------+
  534. | |RTL Partition |Replication |Instances |
  535. +-+--------------+------------+----------+
  536. +-+--------------+------------+----------+
  537. ---------------------------------------------------------------------------------
  538. Start Timing Optimization
  539. ---------------------------------------------------------------------------------
  540. ---------------------------------------------------------------------------------
  541. Start Applying XDC Timing Constraints
  542. ---------------------------------------------------------------------------------
  543. ---------------------------------------------------------------------------------
  544. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
  545. ---------------------------------------------------------------------------------
  546. ---------------------------------------------------------------------------------
  547. Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1354.902 ; gain = 472.980 ; free physical = 140 ; free virtual = 3386
  548. ---------------------------------------------------------------------------------
  549. Report RTL Partitions:
  550. +-+--------------+------------+----------+
  551. | |RTL Partition |Replication |Instances |
  552. +-+--------------+------------+----------+
  553. +-+--------------+------------+----------+
  554. ---------------------------------------------------------------------------------
  555. Start Technology Mapping
  556. ---------------------------------------------------------------------------------
  557. ---------------------------------------------------------------------------------
  558. Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  559. ---------------------------------------------------------------------------------
  560. Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  561. Report RTL Partitions:
  562. +-+--------------+------------+----------+
  563. | |RTL Partition |Replication |Instances |
  564. +-+--------------+------------+----------+
  565. +-+--------------+------------+----------+
  566. Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 132 ; free virtual = 3378
  567. ---------------------------------------------------------------------------------
  568. Start IO Insertion
  569. ---------------------------------------------------------------------------------
  570. ---------------------------------------------------------------------------------
  571. Start Flattening Before IO Insertion
  572. ---------------------------------------------------------------------------------
  573. ---------------------------------------------------------------------------------
  574. Finished Flattening Before IO Insertion
  575. ---------------------------------------------------------------------------------
  576. ---------------------------------------------------------------------------------
  577. Start Final Netlist Cleanup
  578. ---------------------------------------------------------------------------------
  579. ---------------------------------------------------------------------------------
  580. Finished Final Netlist Cleanup
  581. ---------------------------------------------------------------------------------
  582. ---------------------------------------------------------------------------------
  583. Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  584. ---------------------------------------------------------------------------------
  585. Report Check Netlist:
  586. +------+------------------+-------+---------+-------+------------------+
  587. | |Item |Errors |Warnings |Status |Description |
  588. +------+------------------+-------+---------+-------+------------------+
  589. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  590. +------+------------------+-------+---------+-------+------------------+
  591. ---------------------------------------------------------------------------------
  592. Start Renaming Generated Instances
  593. ---------------------------------------------------------------------------------
  594. ---------------------------------------------------------------------------------
  595. Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  596. ---------------------------------------------------------------------------------
  597. Report RTL Partitions:
  598. +-+--------------+------------+----------+
  599. | |RTL Partition |Replication |Instances |
  600. +-+--------------+------------+----------+
  601. +-+--------------+------------+----------+
  602. ---------------------------------------------------------------------------------
  603. Start Rebuilding User Hierarchy
  604. ---------------------------------------------------------------------------------
  605. ---------------------------------------------------------------------------------
  606. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  607. ---------------------------------------------------------------------------------
  608. ---------------------------------------------------------------------------------
  609. Start Renaming Generated Ports
  610. ---------------------------------------------------------------------------------
  611. ---------------------------------------------------------------------------------
  612. Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  613. ---------------------------------------------------------------------------------
  614. ---------------------------------------------------------------------------------
  615. Start Handling Custom Attributes
  616. ---------------------------------------------------------------------------------
  617. ---------------------------------------------------------------------------------
  618. Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  619. ---------------------------------------------------------------------------------
  620. ---------------------------------------------------------------------------------
  621. Start Renaming Generated Nets
  622. ---------------------------------------------------------------------------------
  623. ---------------------------------------------------------------------------------
  624. Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  625. ---------------------------------------------------------------------------------
  626. ---------------------------------------------------------------------------------
  627. Start Writing Synthesis Report
  628. ---------------------------------------------------------------------------------
  629. Report BlackBoxes:
  630. +------+--------------+----------+
  631. | |BlackBox name |Instances |
  632. +------+--------------+----------+
  633. |1 |system | 1|
  634. +------+--------------+----------+
  635. Report Cell Usage:
  636. +------+-------+------+
  637. | |Cell |Count |
  638. +------+-------+------+
  639. |1 |system | 1|
  640. +------+-------+------+
  641. Report Instance Areas:
  642. +------+---------+-------+------+
  643. | |Instance |Module |Cells |
  644. +------+---------+-------+------+
  645. |1 |top | | 0|
  646. +------+---------+-------+------+
  647. ---------------------------------------------------------------------------------
  648. Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.918 ; gain = 481.996 ; free physical = 131 ; free virtual = 3377
  649. ---------------------------------------------------------------------------------
  650. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
  651. Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1363.918 ; gain = 104.434 ; free physical = 131 ; free virtual = 3377
  652. Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1363.926 ; gain = 482.004 ; free physical = 131 ; free virtual = 3377
  653. INFO: [Project 1-571] Translating synthesized netlist
  654. INFO: [Project 1-570] Preparing netlist for logic optimization
  655. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  656. INFO: [Project 1-111] Unisim Transformation Summary:
  657. No Unisim elements were transformed.
  658. INFO: [Common 17-83] Releasing license: Synthesis
  659. 13 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  660. synth_design completed successfully
  661. synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1364.918 ; gain = 410.457 ; free physical = 130 ; free virtual = 3377
  662. report_utilization: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1372.922 ; gain = 0.000 ; free physical = 129 ; free virtual = 3377
  663. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:31 2017...
  664. [Tue Jan 3 15:12:34 2017] synth_1 finished
  665. wait_on_run: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:27 . Memory (MB): peak = 1070.695 ; gain = 8.000 ; free physical = 619 ; free virtual = 3868
  666. ## launch_runs impl_1
  667. [Tue Jan 3 15:12:34 2017] Launched impl_1...
  668. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
  669. ## wait_on_run impl_1
  670. [Tue Jan 3 15:12:34 2017] Waiting for impl_1 to finish...
  671. *** Running vivado
  672. with args -log system_wrapper.vdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
  673. ****** Vivado v2016.2 (64-bit)
  674. **** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
  675. **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
  676. ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
  677. source system_wrapper.tcl -notrace
  678. Design is defaulting to srcset: sources_1
  679. Design is defaulting to constrset: constrs_1
  680. INFO: [Project 1-479] Netlist was created with Vivado 2016.2
  681. INFO: [Device 21-403] Loading part xc7z020clg400-1
  682. INFO: [Project 1-570] Preparing netlist for logic optimization
  683. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  684. CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
  685. INFO: [Project 1-111] Unisim Transformation Summary:
  686. No Unisim elements were transformed.
  687. Command: opt_design
  688. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  689. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  690. Running DRC as a precondition to command opt_design
  691. Starting DRC Task
  692. INFO: [DRC 23-27] Running DRC with 8 threads
  693. ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
  694. INFO: [Project 1-461] DRC finished with 1 Errors
  695. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  696. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
  697. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1280.484 ; gain = 66.031 ; free physical = 222 ; free virtual = 3489
  698. INFO: [Common 17-83] Releasing license: Implementation
  699. 10 Infos, 0 Warnings, 1 Critical Warnings and 2 Errors encountered.
  700. opt_design failed
  701. ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
  702. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:44 2017...
  703. [Tue Jan 3 15:12:46 2017] impl_1 finished
  704. wait_on_run: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:12 . Memory (MB): peak = 1070.695 ; gain = 0.000 ; free physical = 597 ; free virtual = 3865
  705. ## launch_runs impl_1 -to_step write_bitstream
  706. [Tue Jan 3 15:12:46 2017] Launched impl_1...
  707. Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/oh/src/accelerator/fpga/system.runs/impl_1/runme.log
  708. ## wait_on_run impl_1
  709. [Tue Jan 3 15:12:46 2017] Waiting for impl_1 to finish...
  710. [Tue Jan 3 15:12:46 2017] impl_1 finished
  711. INFO: [Common 17-206] Exiting Vivado at Tue Jan 3 15:12:46 2017...
  712. [ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit
  713. cp: cannot stat 'system_wrapper.bit.bin': No such file or directory
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