1. // Adapted from http://zipcpu.com/blog/2017/06/08/simple-scope.html
  2. module internal_logic_analyzer(); // Used to **log** or write internal FPGA signals into memory
  3. parameter DATA_WIDTH = 32;
  4. parameter ADDR_WIDTH = 32;
  5. parameter HOLDOFF_WIDTH = 32;
  6. input clk, reset, i_trigger; // clock, reset(to signal start writing) and trigger(to signal stop writing) input signals
  7. input [(HOLDOFF_WIDTH-1) : 0] i_holdoff; // a programmable user holdoff value that determines how much more to write upon receiving trigger signal before stopping memory write
  8. input [(DATA_WIDTH-1) : 0] i_data; // connected to internal FPGA signals of interest
  9. output[(DATA_WIDTH-1) : 0] o_data; // to be viewed using gtkwave
  10. wire [(ADDR_WIDTH-1) : 0] waddr; // memory address for writing purpose
  11. wire primed; // '1' indicates memory has been initialized, '0' indicates otherwise
  12. wire stopped; // just a stop flag for stopping memory writing
  13. // Writing into a slightly modified circular buffer with no read pointer concept
  14. write_mem wr (.clk(clk), .reset(reset), .write_enable(!stopped), .i_data(i_data), .waddr(waddr), .primed(primed));
  15. // Reading from a slightly modified circular buffer with no read pointer concept
  16. read_mem rd (.clk(clk), .reset(reset), .read_enable(stopped), .waddr(waddr), .o_data(o_data));
  17. // Determines when to (stop writing and then start reading)
  18. stop st (.clk(clk), .reset(reset), .waddr(waddr), .primed(primed), .i_trigger(i_trigger), .i_holdoff(i_holdoff), .stopped(stopped));
  19. endmodule
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