1. 2355573 addMarkerCreateDelta causes Virtuoso Visualization and Analysis XL to exit unexpectedly
  2. 2355570 axlRunSimulation fails on assertion
  3. 2354184 Cannot edit dc sweep analysis when the Dynamic Parameter option is enabled with transient analysis
  4. 2352987 Virtuoso exits unexpectedly due to array bounds write issue
  5. 2352981 Virtuoso exits unexpectedly during constraints refresh
  6. 2351930 Pin Stretching is not visible when WSPs are disabled
  7. 2351258 saveGraphImage() plots an empty waveform after awvLoadWindow()
  8. 2348930 Virtuoso exits unexpectedly when performing C extraction in EAD in ICADVM20.1
  9. 2348902 Cannot set minimum and maximum voltage values for a single bus bit
  10. 2348189 Virtuoso exits unexpectedly due to invalid object referenced during extraction
  11. 2347644 Virtuoso exits unexpectedly when performing RC extraction in EAD
  12. 2347339 Virtuoso exits unexpectedly due to memory allocation issue
  13. 2346239 ADE Explorer returns incorrect values during corners analysis, but the results in ADE Assembler are fine
  14. 2345829 Using the SKILL function verifExportSnapshotsToExcel with a read-only cellview reports a segmentation fault error
  15. 2343853 Cross-Fabric EM for Package and IC: EM Assistant not enabled
  16. 2343637 Incorrect behavior of chop in minSpacing mode when multiple objects are chopped
  17. 2343631 Virtuoso exits unexpectedly in the Generate Constraints step of the Automated Device Placement and Routing flow
  18. 2343497 Creating Design Intent on different schematic views of the same cell causes Virtuoso to exit unexpectedly
  19. 2343482 Virtuoso exits unexpectedly in ctuRouteSegment::setPts
  20. 2342778 Virtuoso exits unexpectedly when selecting the destination TILP in the Propagate Bumps command
  21. 2342534 Creating Design Intent on different schematic views of the same cell causes Virtuoso to exit unexpectedly
  22. 2342249 lxNavigatorCustomiser hangs when there are a large number of mosaics in a design
  23. 2342142 Cannot zoom to some of the labels generated using the Create Labels/Markers From Net Voltages menu option
  24. 2342136 vdrCreateVoltageLabelEx SKILL API and Create Labels/Markers From Simulation Voltages do not generate some labels
  25. 2342078 Opening a layout design takes a long time due to ciElaborator::elaborateCache
  26. 2342071 Corner Config Sweep with LSCS creates very long directory names
  27. 2341307 maestro view displays incorrect result for DSPF simulation when PSF data is correct
  28. 2339356 The Output Setup tab in a maestro view sometimes becomes uneditable
  29. 2339110 Double-click on a cell does not respond after multiple edits
  30. 2338772 AMS fails to create a netlist when using a smart view extraction format
  31. 2337538 Chopping pathSeg is not allowed
  32. 2337377 Losing a fault device while sampling a given set of faults with multiple devices
  33. 2337040 The temperature variable set in Reliability Analysis Editor is not used in the netlist
  34. 2336960 Issues with diffpair routing matching lengths
  35. 2336916 Updating cellview while using the 'FirstAccessLib' trigger fails in ICADVM18.1
  36. 2336877 Temperature in stress test overridden by temperature in corner
  37. 2336752 Virtuoso Visualization and Analysis XL shows wrong results for digital signals
  38. 2336707 Simulation runs in Virtuoso ADE Verifier remain in the running state for a long time if multiple runs are started in parallel
  39. 2336521 Virtuoso exits unexpectedly in ctpStripeRouter::createStoredSegment
  40. 2335906 ADE Assembler does not export evalType to CSV
  41. 2335223 Virtuoso exits unexpectedly while expanding Design Intent in schematic Navigator
  42. 2335158 Repeated copy of tar files results in slowness even when running with Optimize Single Point Run
  43. 2334897 PG function is not tracing to base if both regulated and base supplies are specified as inputs at top level
  44. 2334426 Environment variable not defined error is shown while adding an implementation in ADE Verifier
  45. 2334364 _axlUpdateDesign in function _axlConfigureForADE takes 28 seconds when Optimize Single Point Run is enabled
  46. 2334305 Editing two schematic views of the same cell name and then closing one of them causes Virtuoso to exit unexpectedly
  47. 2334155 AMS UNL: Netlisting error if iterated instance with input bus bound to extracted view
  48. 2334290 Editing two schematic views of the same cell name and then closing one of them causes Virtuoso to exit unexpectedly
  49. 2334066 Extractor does not warn or stop at wrong power switch definition and extracts incorrect switch_function instead
  50. 2334044 Switch function is extracted incorrectly
  51. 2334041 The isolation_enable_condition contains supply nets connected to bias bins of isolation cell in the backtrace path
  52. 2334030 Unable to backtrace through an isolation cell
  53. 2333669 Virtuoso Visualization and Analysis XL exits unexpectedly after being opened from Virtuoso ADE Verifier
  54. 2333642 The current estimation mode is incorrect when starting from shapes which are inside a group and connected to devices pins
  55. 2333580 Output expressions with EvalType 'sweeps' are not exported correctly to CSV
  56. 2333429 The Outputs Setup table scrolls to the selected item when the Plot or Save check box is toggled for another output
  57. 2333389 vmin/vmax results are not exported to a CSV file when only a single signal is selected
  58. 2333275 Wire Assistant layer panel is showing duplicate metal layer entries with different width and spacing
  59. 2333202 Routability Check incorrectly flags inaccessible pins for many nets, which leads to routing failure
  60. 2331816 Closing a layout causes Virtuoso to go into an infinite loop
  61. 2331807 Pin Accessibility Checker displays an error on socket or refused connection between Innovus and Virtuoso while parsing the violation report
  62. 2331792 When disabling Delete Shield Only, the nets and shields are deleted but the mesh via are not deleted
  63. 2331748 Virtuoso exits unexpectedly in leTechLPPs::getAllValidLPPsFromTech when kill is used in CIW
  64. 2331463 The vpsbatch command does not report internal nets in IR reports when using 'net coupled_nets=[]' in the EMIR configuration file
  65. 2331435 Incorrect PG_function with intermediate supply node for a few pins
  66. 2331189 yp function has a variable omitted from let which causes error due to write protected function
  67. 2331034 Long-term xrun simulation causes ADE Assembler to report failed simulation points and the results database to report 'unknown error'
  68. 2330942 PG_function not getting traced through power switch
  69. 2330886 Suspend and Resume option is not available while troubleshooting a Point run with LSCS when using the 'command' job distribution method
  70. 2330697 Abstract Generator suppresses warning messages for database call failure
  71. 2330581 LSCS: Parallel Num Processors field is reset to blank after running a simulation
  72. 2330501 Virtuoso Power Manager to use the power switch output net as related power pin in case of handling equivalent nets with same priority
  73. 2330489 Signal names 'vdd' and 'gnd' are hardcoded as power and ground nets and cannot be netlisted as wires
  74. 2330368 ADE Explorer not running selected corners
  75. 2330278 Problem with scaling of path segments during XStream In translation.
  76. 2329913 Isolation enable condition is printing internal supply net, connected instance, and VDD name
  77. 2329571 Single via to stacked via conversion in property editor resets to via default parameters
  78. 2329315 Fix or retire maestro.setupdb automaticallyCleanupScriptsAndTranslateHistoryStateFiles
  79. 2328980 For a string parameter value ADE Assembler throws ERROR (ASSEMBLER-1706): The requested reference value not in design space
  80. 2328925 Routing over blockage issue observed in ICADVM20.1 EA23 build version
  81. 2328827 Virtuoso exits unexpectedly during AMS netlist creation due to an invalid character used in the project directory
  82. 2328297 Issue with creating note text using the schHiCreateNoteLabel SKILL API
  83. 2328079 axlRunSimulation fails on assertion
  84. 2327910 *WARNING* (LE-103927): Chop operation failed on corner of a pathSeg in IC6.1.8 and changes object type to polygon
  85. 2327897 maeSensEnableDesignVariation does not work on a newly created view
  86. 2327546 Instance or net probing issue for a check or assert when the device is not present in schematic
  87. 2327542 Three times performance degradation observed while zooming out
  88. 2326266 A dependent design variable is not assigned value from Corners Setup for the first design point in ADE Explorer
  89. 2326251 Virtuoso quits unexpectedly while setting Constraint Group from Layout Editor Options form
  90. 2325951 Virtuoso exits unexpectedly due to a segmentation fault of leHiSave in ctuDesignsSyncFromOA
  91. 2325878 Virtuoso exits unexpectedly when deleting read-only history
  92. 2325813 Virtuoso exits unexpectedly in ctuObject::foreignObject
  93. 2325804 Virtuoso exits unexpectedly in ctuRouteSegment::_setCustomNoTransNoZonePts
  94. 2325567 Modify the list format for the create_pst attribute
  95. 2325518 License for Virtuoso Schematic Editor Verilog Interface remains checked out if netlisting fails in Virtuoso SystemVerilog Netlister
  96. 2325222 elaborateUsingConfig is not working as expected
  97. 2324508 Die wirebonds do not snap to fingers of package layout even though there is no connectivity
  98. 2324213 Virtuoso exits unexpectedly in mapiOpenCellViewByType
  99. 2324071 Navigator Assistant becomes unresponsive when trying to set current path
  100. 2324006 Virtuoso Power Manager exporting incorrect value in the control_port option for the create_power_switch rules
  101. 2323840 Virtuoso exits unexpectedly while creating Vsync markers
  102. 2323835 Improve message of layout compare when scalarinst not available in the other design
  103. 2323778 ocxnlUpdatePointVariable() function in a pre-run script does not work if the global variable uses an expression
  104. 2323712 The sprintf syntax form does not work as expected for a global variable after IC6.1.8 ISR11
  105. 2323432 Sorting of columns in Detail-Transpose view does not work on filtered data
  106. 2323069 Setting DSPF file path from new EMIR UI does not populate DSPF path in UI when simulator is AMS
  107. 2322915 Missing level shifter not reported when gate is driven by supply net
  108. 2322722 Remove the Tie Shield extra via connection stubs
  109. 2322167 lxHiCreateInstFromSch SKILL API is slow
  110. 2322164 Virtuoso exhibits poor performance when moving between layout tabs
  111. 2322154 Cannot chop a pathSeg into a polygon in Virtuoso 6.18, the leChopPreservePathSeg=nil does not work now
  112. 2322121 Virtuoso exits unexpectedly in API mapiOpenCellViewByType
  113. 2321950 Using the 'Delete Run Summary Data' command puts a lock on the implementation run summary data file
  114. 2321796 Virtuoso exits unexpectedly while trying to import a file using XStream In GUI
  115. 2321788 The Selected ParamSet command to expand selected corners in the corner's setup does not work if sweep value is duplicated
  116. 2321243 Library ECO on import changes the SMD footprint
  117. 2321073 Short created by auto via with m1 inside instance
  118. 2321046 Tied-off ports should not be set to is_analog=t, they should be set as digital without single rail cell registration
  119. 2321043 Incorrect related power pin not processed correctly for shorted supplies and equivalent nets
  120. 2321038 PG_function has internal power connections that are not related to any power pin of boundary port
  121. 2321036 Internal power becomes primary power in specific cases with shorted devices
  122. 2320802 Manual scaling does not work if Step Size is enabled in the Dependent Axis properties
  123. 2320706 HDL file information disappears from the AMS netlist generated through ADE Explorer
  124. 2320617 Signals from the last PSFXL segment cannot be plotted in the waveform window unless the interactive SimVision session is closed
  125. 2320475 Virtuoso SiP Generate From Source flow should only uniquify cell names where duplicate cell names are referencing different cellviews
  126. 2320333 Duplicate checklimit statement inside reliability block gives an error SFE-401 during simulation
  127. 2320241 HDL Package Setup settings cause recompilation when C code is used in -makelib
  128. 2320215 Drop-down menu of the Spec column is not accessible after double-clicking a Spec cell
  129. 2320176 Spelling mistake in ADE ASSEMBLER-3002 error message
  130. 2319700 Wirebond connectivity between die bond pads is not established in Layout XL connectivity extractor for Virtuoso RF Solution
  131. 2319551 schHiReturn SKILL API is slow
  132. 2319345 The slots on short Z wire segments should be square instead of rectangular slots
  133. 2318753 The Outputs Setup table scrolls to the top when an output or expression is enabled or disabled
  134. 2318671 Mesh routing in Pin to Trunk router does not shield the whole net
  135. 2318409 Wrong y axis for digital signals in Virtuoso Visualization and Analysis XL IC6.1.8 ISR13
  136. 2318173 Chop command in line mode does not create the same space as drawing purpose for metal fill
  137. 2318165 Waveform output causing Spectre to exit unexpectedly
  138. 2318021 Generate Selected From Layout using Virtuoso Photonics option generates non-editable schematic objects that cannot be deleted
  139. 2317815 Virtuoso exits unexpectedly due to incorrect Ctrl-C hidden declaration
  140. 2317683 Virtuoso exits unexpectedly in axlDataViewWidget
  141. 2317316 Enhance Virtuoso Power Manager to identify PG_function base supply using additional top-level pin directions
  142. 2317312 Virtuoso Power Manager should not be printing internal_power in pg_function
  143. 2317248 Top-level unconnected pin with direction output becomes primary power pin in Virtuoso Power Manager
  144. 2317014 DCOP expressions are not evaluated through Calculator
  145. 2316687 Saving Track Pattern setting/preferences
  146. 2316520 minCutRouting constraint does not work with cutClass for via to external metal spacing
  147. 2316466 writeOA: SiP to Schematic results in a stacktrace with the given .sip file
  148. 2315911 Virtuoso exits unexpectedly while abutting Modgens
  149. 2315851 Virtuoso exits unexpectedly while working with Modgens
  150. 2315709 Line chop with justification as center creates off-grid results when spacing rule is an odd multiple of grid
  151. 2314593 Virtuoso exits unexpectedly when using Property Editor
  152. 2314527 Check bump alignment to issue log file message despite positive result
  153. 2314482 Issues found when the preservePins option is used with the dbFlattenInst2 SKILL function
  154. 2314424 ccpDFIIchecker does not see the DPUPerUU of the base reference library in the ITDB technology reference library
  155. 2313598 postFunc for flowchart step asiStartSimulator does not get called in LSCS; works fine in ICRP
  156. 2313546 Support CSV export from Detail results view to include full parameter lib/cell/view path
  157. 2313915 AMS UNL: Netlist error when iterated instance having bus pin is set to extracted view
  158. 2312987 Chop command in line mode does not create the same space as drawing purpose for metal fill
  159. 2312816 Virtuoso Space-based Router is creating minLength violation when dropping a via
  160. 2312238 cdsGenVia stacked via top rows and columns are not editable in the Property Editor
  161. 2311474 Infix does not work after running the Edit In Place command for a synchronous clone
  162. 2310612 Virtuoso exits unexpectedly when right-clicking a blank corner name
  163. 2309992 Allegro Import translator should translate Allegro DBU grid to Virtuoso manufacturing grid
  164. 2309816 Create stranded wire does not correct spacing value when defined spacing violates allowedSpacingRanges constraint
  165. 2309787 Wire width is getting dynamically updated while creating stranded wire
  166. 2309732 Annotation Browser to offer easy and in-context error browsing mechanism
  167. 2309538 pm0 jitterevent statement missing from OCEAN state file
  168. 2309455 Create Stranded Wire does not respect allowedSpacingRanges constraint after dropping a via
  169. 2309082 Instance or net probing issue for a check or assert when the device is not present in schematic
  170. 2308951 Add waveform comparison capabilities in Virtuoso Visualization and Analysis XL
  171. 2308747 Undesired output in the extracted Liberty files in subsequent runs for the given testcase
  172. 2305498 Virtuoso exits unexpectedly when the number of histories running in parallel is more than the value of saveLastNReadOnlyHistoryEntries
  173. 2303978 Smart extracted view creation issues ERROR (SMARTVIEW-11001)
  174. 2303149 Export Data to CSV gives incorrect results when a row is missing from statResultValue table
  175. 2303110 Import/Export Outputs from/to CSV does not work with fault expressions
  176. 2301631 minEdgeAdjacentLength does not work consistently in AND groups
  177. 2300749 Related power pin not getting extracted if input pin of standard cell is connected to source or drain of a MOS device
  178. 2300885 Shape except for channel layer is displayed in heatmap of channel layer only
  179. 2300583 Pin Connectivity form expands to 'All' mode after creating 'Make Strong Connect Group'
  180. 2299507 Incorrect pin order generated during auCDL netlisting
  181. 2298937 DECAP insertion flow not working in ICADVM18.1 ISR12
  182. 2298115 Virtuoso Power Manager missing related power pin for a few cases
  183. 2297700 Virtuoso quits unexpectedly when the Verify Design option is used
  184. 2297088 ADE Assembler generates wrong dyn_subcktpwr syntax
  185. 2296150 The final Monte Carlo run does not use the improved parameter set
  186. 2295896 Cannot chop a piece or corner off from a pathSeg in Virtuoso IC6.1.8, the leChopPreservePathSeg=nil does not work
  187. 2294518 Should ignore the mosaic type of bumps in the Edit-In-Concert flow
  188. 2293010 In AMS Designer, instance-based MTS setup is not working
  189. 2291037 ctu shape fracturing taking long time when running delete routing and global routing
  190. 2290454 The Voltus-Fi SHE flow does not work on 45nm process nodes
  191. 2289265 Infix feature not working as expected with some commands
  192. 2288466 runams stops responding when a non-existing connect library is defined in connectRules.il
  193. 2287309 Local Optimization does not work as expected in ADE Assembler
  194. 2285341 Abstract Generator does not pass the coreSpacer cellType attribute from layout to LEF
  195. 2285007 Measurements exported from ADE Assembler do not save EvalType 'all' and 'sweeps'
  196. 2282923 Pattern parameter data for the Analog Library symbol 'vsource' is interpreted incorrectly during netlisting
  197. 2282755 Virtuoso exits unexpectedly in axlSetOffsetDataOnCornerTable
  198. 2282249 validPurposes in virtuosoDefaultExtractorSetup causes extraction shorts
  199. 2281377 OpenGL failed to start on RH6.9 and RH7 because libglut.so is missing
  200. 2279953 awvSetSmithYLimit & awvSetSmithXLimit do not work for Circular graphs
  201. 2279857 Virtuoso Space-based Router is routing inconsistently when repeating on same design
  202. 2279822 waveform compare does not work when Override Global Tolerance Settings is selected and another maestro view is used as reference
  203. 2277295 eval error happens randomly when using calcVal in ADE Assembler
  204. 2270885 Reference netlist flow fails to copy netlist with error 'cpDataDir call returned 0'
  205. 2270628 Warnings issued when Edit-In-Concert is clicked
  206. 2268705 Updating of subwindows using awvUpdateWindow(awvGetCurrentWindow()) or awvUpdateAllWindows not working
  207. 2268286 In ICADVM18.1 ISR11, Virtuoso Space-based Router leaves open nets
  208. 2267444 Virtuoso exits unexpectedly in axlDataViewWidget
  209. 2265708 Virtuoso exits unexpectedly in axlSetOffsetDataOnCornerTable
  210. 2262784 Warnings issued for the read-only technology library while opening cellview in Virtuoso RF Solution with libImport libraries
  211. 2260807 An unsaved change in config view is getting reflected in MTS Options form
  212. 2252376 Deleting object with an attached pin does not clean up empty net terminal name
  213. 2250727 Row height does not adjust correctly in user-specified mode
  214. 2250301 Appending another waveform after using a plotting template pushes out existing waveform
  215. 2245193 Net Tracer is not capturing all the via types used in the original layout
  216. 2218697 How to save the terminal voltage probing for an estimated view in PAD flow?
  217. 2214197 Support Waveform Compare feature with time tolerance
  218. 2209855 saveGraphImage() plotting incomplete data
  219. 2198128 Virtuoso processes indefinitely while trying to select or edit instances in the Property Editor
  220. 2189192 Results cannot be sorted in the 'Detail-Transpose' results view
  221. 2126206 In ICADVM18.1 ISR4, Virtuoso Space-based Router wrongly extends the trunk and causes minEndOfLineSpacing error
  222. 2077769 In maestro cellviews, the Copy from Cellview command for Design Variables is very slow
  223. 2062042 In ICADVM18.1 ISR1, Virtuoso Space-based Router performs bad routing when ignore shielding layer option is not used
  224. 2043014 Create test copy in maestro view must not open new tabs in Virtuoso Visualization and Analysis XL
  225. 2025943 Unable to open a design with a text-on-top configuration
  226. 2024101 Clicking the 'Refresh Setup Library with current changes' button does not show the latest changes
  227. 1949615 Question about Improve Yield algorithm
  228. 1948499 EvalType does not appear in the outputs.csv file
  229. 1943189 Using saveGraphImage to save .png output of statistical results loses the histogram bins
  230. 1872403 The mapping variable hnlBusNamePrefix is not working as expected during NC-Verilog netlisting
  231. 1856655 Exporting and then importing back outputs loses measurement across sweeps and all settings
  232. 1853478 EvalType does not appear in the outputs.csv file
  233. 1811008 Navigator is slow to build cell list on design with many mosaics
  234. 1754434 Virtuoso exits unexpectedly when a pin net name is updated in the Property Editor
  235. 1725949 Avoid reporting violations at core and IO devices to ensure reporting device-specific input voltage tolerance
  236. 1138865 Virtuoso exits unexpectedly when using the Stretch command